Memory with modifiable address map

• US 20060149918A1
• Filed: 12/30/2005
• Published: 07/06/2006
• Est. Priority Date: 12/30/2004
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Richardson, Ray, O'Connor, Dennis M., Fullerton, Mark N., Rudelic, John C.
• Application Number:
  US11/323,473
• Publication Number:
  US 20060149918A1
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

A memory device includes a flag register to modify the address map of the memory device based on the state of an input node on the memory device.

Claims

1. A memory device comprising:

a plurality of memory blocks;

a plurality of programmable flags, wherein each of the memory blocks is associated with a corresponding one of the plurality of programmable flags; and

a control circuit to gate access to each of the plurality of memory blocks based on a state of the corresponding programmable flag and a state of an input to the memory device.

2. The memory device of claim 1 wherein the control circuit modifies an address map of the memory device into two mutually exclusive blocks of memory based on the state of the input.

3. The memory device of claim 1 wherein the control circuit modifies an address map of the memory device into a first map including all of the plurality of memory blocks, and into a second map including a subset of the plurality of memory blocks.

4. The memory device of claim 1 wherein the memory device comprises a nonvolatile memory.

5. The memory device of claim 4 wherein the memory device comprises a FLASH memory device.

6. An integrated circuit comprising a memory device having a plurality of blocks conditionally visible in an address space based on a logical state of an input node and based on flag values programmed in the memory device, wherein each of the flag values corresponds to one of the plurality of blocks.

7. The integrated circuit of claim 6 wherein each of the plurality of blocks is visible in the address space when the logical state of the input node matches a corresponding flag value.

8. The integrated circuit of claim 6 wherein each of the plurality of blocks is not visible in the address space when the logical state of the input node does not match a corresponding flag value.

9. The integrated circuit of claim 6 wherein all of the plurality of blocks are visible in the address space when the logical state of the input node is in a first state, and only blocks having associated flag values matching a second state are visible when the logical state of the input node is in the second state.

10. The integrated circuit of claim 6 further comprising a memory controller coupled to provide a secure/non-secure indication on the input node of the memory device.

11. The integrated circuit of claim 6 further comprising a memory controller coupled to provide a user/supervisor indication on the input node of the memory device.

12. The integrated circuit of claim 6 further comprising a memory controller comprising a memory partitioning mechanism to partition the memory device into secure and non-secure partitions wherein the memory partitioning mechanism comprises at least one register to define a range of locations in the memory device.

13. A method comprising:

receiving values for programmable flags within a memory device to assign memory blocks to one of two privilege modes;

providing a first address map when the memory device is accessed when an external node on the memory device is set to a first of the two privilege modes; and

providing a second address map when the memory device is accessed when the external node on the memory device is set to a second of the two privilege modes.

14. The method of claim 13 wherein the first address map is a subset of the second address map.

15. The method of claim 13 wherein the first address map and second address map are mutually exclusive.

16. The method of claim 13 further comprising receiving configuration information to set address map behavior, wherein in a first behavior, the first address map is a subset of the second address map, and in a second behavior, the first address map and the second address map are mutually exclusive.

17. A system comprising:

an antenna;

a receiver coupled to the antenna;

a processor coupled to the receiver; and

a memory device coupled to the processor, the memory device comprising a plurality of memory blocks, a plurality of programmable flags, wherein each of the memory blocks is associated with a corresponding one of the plurality of programmable flags, and a control circuit to gate access to each of the plurality of memory blocks based on a state of the corresponding programmable flag and a state of an input to the memory device.

18. The system of claim 17 wherein the control circuit modifies an address map of the memory device into two mutually exclusive blocks of memory based on the state of the input.

19. The system of claim 17 wherein the control circuit modifies an address map of the memory device into a first map including all of the plurality of memory blocks, and into a second map including a subset of the plurality of memory blocks.

20. The system of claim 17 wherein the memory device comprises a nonvolatile memory.