Microprocessor optimized for algorithmic processing

• US 20060149923A1
• Filed: 12/08/2004
• Published: 07/06/2006
• Est. Priority Date: 12/08/2004
• Status: Abandoned Application

• Current Assignee: Paul Goodwin
• Original Assignee: Staktek Group L.P. (Entorian Technologies)
• Inventors: Goodwin, Paul
• Application Number:
  US11/007,745
• Publication Number:
  US 20060149923A1
• Time in Patent Office: Days
• US Class Current: 712/11
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

Provided is a microprocessor optimized for algorithmic processing for accelerating algorithm processing through a closely coupled set of parallel sub-processing elements. The device includes a primary processor, one or more subprocessors and an interconnecting buss. The buss is preferably a crossbar buss. The primary processor is preferably a pipelined CPU with additional logic to support algorithm processing. The crossbar buss allows the data memory to function as the data memory in the CPU, and provides paths to configure and initialize the algorithm subprocessors and to retrieve results from the subprocessors. The subprocessors are processing elements that execute segments of code on blocks of data. Preferably, the subprocessors are reconfigurable to optimize performance for the algorithm being executed.

Claims

1. A processing unit comprising:

a primary processor having an arithmetic logic unit, a data memory cache, one or more subprocessor control and status registers; and

a crossbar buss associated with the primary processor that interconnects the arithmetic logic unit to the data memory cache, the crossbar buss having a plurality of ports and being capable of providing multiple connection paths between respective selected sets of ports at the same time;

one or more subprocessors interconnected to the crossbar buss, each of the one or more subprocessors having a data memory store and an instruction memory store, the crossbar buss connected to the data memory store and to the instruction memory store.

2. The processing unit of claim 1 further comprising one or more data memory control registers on the primary processor, the data memory control registers operative to configure the crossbar buss to connect the arithmetic logic unit to a selected one or more of a group comprising the data memory cache and the data memory stores of the one or more subprocessors.

3. The processing unit of claim 2 in which the one or more data memory control registers are operative to configure the crossbar buss to connect the arithmetic logic unit to a selected one or more instruction memory stores of the one or more subprocessors.

4. The processing unit of claim 1 in which the one or more subprocessors are re-configurable logic elements.

5. The processing unit of claim 1 in which the crossbar buss has a plurality of data buss ports, there being enough data buss ports to connect to at least one buss for each of the one or more subprocessors.

6. The processing unit of claim 1 in which the crossbar buss has a plurality of data buss ports, there being enough data buss ports to connect to at least one memory buss for each of the one or more subprocessors and at least one instruction memory buss for each of the one or more subprocessors.

7. The processing unit of claim 1 further comprising an address decoder attached to the crossbar buss, the address decoder for generating enable signals for one or more of the subprocessors.

8. The processing unit of claim 1 further comprising an expansion processor buss for connecting to an expansion processor, the expansion processor buss being connected to the crossbar buss.

9. The processing unit of claim 1 further comprising a read data multiplexer on the crossbar buss.

10. A processing unit comprising:

a primary processor having an arithmetic logic unit and data memory cache;

one or more subprocessors;

one or more memory data stores, each of the memory data stores associated with at least one of the one or more subprocessors;

a buss connecting the arithmetic logic unit of the primary processor to the data memory cache of the primary processor and to the one or more memory data stores.

11. The processing unit of claim 10 in which the buss is a crossbar buss.

12. The processing unit of claim 10 in which the buss is a crossbar buss and in which each of the memory data stores is associated with at least one of the one or more subprocessors by having one or more data busses connectible to one or more corresponding data busses on the at least one subprocessor though the crossbar buss.

13. The processing unit of claim 10 in which the primary processor has one or more data memory control registers operative to configure the crossbar buss to connect the arithmetic logic unit to a selected one or more instruction memory stores of the one or more subprocessors.

14. The processing unit of claim 10 in which the primary processor has one or more subprocessor control and status registers operative to configure the one or more subprocessors for operation.

15. The processing unit of claim 11 further comprising a read data multiplexer on the crossbar buss.

16. The processing unit of claim 11 further comprising an address decoder on the crossbar buss, the address decoder for generating enable signals for one or more of the subprocessors.

17. A method of processing an algorithm on a multiple-processor system, the method comprising the steps:

connecting, with a crossbar buss, an arithmetic logic unit on a primary processor to a data cache on the primary processor;

connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a first data memory store associated with a first subprocessor;

loading data intended to be processed by the first subprocessor into the first data memory store;

connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a first instruction memory store associated with the first subprocessor;

loading instructions intended to be executed by the first subprocessor into the first instruction memory store;

connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a second data memory store associated with a second subprocessor;

loading data intended to be processed by the second subprocessor into the second data memory store;

connecting, with the crossbar buss, the arithmetic logic unit on the primary processor to a second instruction memory store associated with the second subprocessor;

loading instructions intended to be executed by the second subprocessor into the second instruction memory store.

18. The method of claim 17 further including the step of setting a subprocessor control and status register to activate the first subprocessor.

19. The method of claim 17 further including the step of waiting for an indication in the subprocessor control and status register that the first subprocessor has completed processing the instructions.

20. The method of claim 17 in which the step of connecting the arithmetic logic unit on the primary processor to the first instruction memory store is done simultaneously with the step of connecting the arithmetic logic unit on the primary processor to the second instruction memory store.

21. The method of claim 17 in which the step of loading instructions intended to be executed by the first subprocessor into the first instruction memory store is done simultaneously with the step of loading instructions intended to be executed by the second subprocessor into the second instruction memory store.

22. The method of claim 17 further including the step of reading, by the second subprocessor, algorithmic output data from first data memory store over the crossbar buss.

23. The method of claim 17 further including the step of writing, by the first subprocessor, algorithmic output data to the second data memory store over the crossbar buss.

24. A circuit module comprising:

a processor packaged in a chipscale package, the processor having an arithmetic logic unit, one or more subprocessors, a data memory cache, one or more data memory stores associated with the one or subprocessors, and a crossbar buss associated with the processor and connecting the arithmetic logic unit to the data memory cache and the data memory stores;

flexible circuitry wrapped about the chipscale package to dispose a first portion of the flexible circuitry above the chipscale package and a second portion of the flexible circuitry below the chipscale package;

one or more semiconductor components mounted to the first portion of the flexible circuitry.

25. The circuit module of claim 24 in which the one or more semiconductor components includes at least one memory component, the memory component configured to function as external memory for the processor.

26. The circuit module of claim 24 further comprising a form standard disposed between the flexible circuitry and the chipscale package.