Keep-out clock alignment cycle coherency protection

• US 20060149987A1
• Filed: 12/31/2004
• Published: 07/06/2006
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, S. Reji, Panikkar, Adarsh, Klowden, Daniel S.
• Granted Patent: US 7,346,795 B2
• Time in Patent Office: Days
• US Class Current: 713/401
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

Claims

1. A system comprising:

a plurality of lanes coupling two clock domains, each lane comprising circuitry to;

generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes; and

generate a second signal to signify a lane has been delayed; and

a control circuit coupled with the plurality of lanes, the control circuit to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

2. The system of claim 1 wherein the lanes are multiple bit data lanes.

3. The system of claim 1 wherein the lanes are single bit data lanes.

4. The system of claim 1 wherein the added latency is one clock cycle of latency.

5. The system of claim 4 wherein the one clock cycle of latency is a clock cycle from the slower of the two clock domains.

6. A system according to claim 1 wherein the control circuit resides in the slower clock domain.

7. The system of claim 1 wherein the clock domains have an asynchronous phase relationship.

8. A method to maintain channel cycle coherency for a multiple lane interface coupling two clock domains, the method comprising:

receiving a first signal from at least one of a plurality of lanes, the first signal representing that lane was delayed;

receiving a second signal from at least one different lane representing that different lane has been delayed;

delaying any lane that did not generate a second signal and that would otherwise cause channel cycle incoherency if not delayed.

9. The method of claim 8 further comprising delaying no lanes when all lanes generate a second signal representing each respective lane has been delayed.

10. The method of claim 8 further comprising compensating for clock skew with a variable control that adjusts a parameter for when the first signal is asserted.

11. A method according to claim 10 compensating for clock skew with a variable control wherein the parameter is in clock cycles of the faster clock domain.

12. A method according to claim 11 compensating for clock skew with a variable control further comprising compensating only when skew is larger than one clock cycle of the faster clock domain.

13. The method according to claim 8 wherein delaying any lane that did not generate a second signal involves delaying that lane one clock cycle of the slower of the clock domains.

14. The method according to claim 8 further comprising delaying all lanes other than any lane providing a first signal if no second signal is generated by any lane.

15. An apparatus comprising:

a first element to receive a plurality of first signals and to logically OR the first signals;

an inverting element to receive and invert a second signal;

a second element coupled with the output of the first element and the output of the inverting element and to logically AND the outputs;

a data lane to provide data, the data lane split into a first channel and a second channel, the first channel to provide the same data as a second channel and the second channel to add a delay to the data; and

a multiplexer coupled with the output of the second element, the multiplexer to select between the first channel and the second channel based upon the output of the second element, and to output the data from the selected channel.

16. The apparatus of claim 15 the circuitry to select the delayed second channel when the second signal is asserted high and any one of the plurality of first signals is asserted high.

17. The apparatus of claim 15 wherein the second channel delay is equivalent to one clock cycle.

18. The apparatus of claim 15 wherein the second channel adds delay with a sticky flop.

19. An apparatus according to claim 15, wherein the data lane is a multiple bit data lane.

20. An apparatus according to claim 15, wherein the data lane is a single bit data lane.