Keep-out clock alignment cycle coherency protection
First Claim
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1. A system comprising:
- a plurality of lanes coupling two clock domains, each lane comprising circuitry to;
generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes; and
generate a second signal to signify a lane has been delayed; and
a control circuit coupled with the plurality of lanes, the control circuit to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.
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Abstract
In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.
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Citations
20 Claims
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1. A system comprising:
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a plurality of lanes coupling two clock domains, each lane comprising circuitry to;
generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes; and
generate a second signal to signify a lane has been delayed; and
a control circuit coupled with the plurality of lanes, the control circuit to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method to maintain channel cycle coherency for a multiple lane interface coupling two clock domains, the method comprising:
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receiving a first signal from at least one of a plurality of lanes, the first signal representing that lane was delayed;
receiving a second signal from at least one different lane representing that different lane has been delayed;
delaying any lane that did not generate a second signal and that would otherwise cause channel cycle incoherency if not delayed. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An apparatus comprising:
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a first element to receive a plurality of first signals and to logically OR the first signals;
an inverting element to receive and invert a second signal;
a second element coupled with the output of the first element and the output of the inverting element and to logically AND the outputs;
a data lane to provide data, the data lane split into a first channel and a second channel, the first channel to provide the same data as a second channel and the second channel to add a delay to the data; and
a multiplexer coupled with the output of the second element, the multiplexer to select between the first channel and the second channel based upon the output of the second element, and to output the data from the selected channel. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification