Method and system for correcting soft errors in memory circuit
First Claim
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1. A method for correcting a soft error in a memory circuit during a stand-by mode, the method comprising:
- reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit;
determining whether the read data is a soft error; and
writing a predetermined value to the memory cell if the read data is the soft error.
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Abstract
A method and a system for correcting a soft error in a memory circuit during a stand-by mode are disclosed. According to the disclosure, after reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit in the stand-by mode, it is determined whether the read data is a soft error. If so, a correct value is written to the memory cell if the read data is the soft error.
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Citations
18 Claims
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1. A method for correcting a soft error in a memory circuit during a stand-by mode, the method comprising:
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reading data from at least one memory cell without outputting the read data through an input/output module of the memory circuit;
determining whether the read data is a soft error; and
writing a predetermined value to the memory cell if the read data is the soft error. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for correcting soft errors in a memory circuit, the method comprising:
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generating an initiation signal on a periodic basis when the memory circuit is in a stand-by mode;
reading one or more word values of a set of memory cells in response to the initiation signal without outputting the word values through an input/output module of the memory circuit; and
writing a correct value to the memory cell if any one of the word values is a soft error. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A system for correcting soft errors of a memory circuit, the system comprising:
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a timer for initiating a dummy read cycle when the memory circuit is in a stand-by mode;
an address counter for producing one or more addresses corresponding to one or more memory cells in the memory circuit after the dummy read cycle is initiated; and
an error checking and correcting circuit for reading one or more word values of one or more memory cells based on the addresses generated by the address counter and for writing a correct value to the memory cell if any of the word values is a soft error. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification