Three dimensional integrated circuits

• US 20060150137A1
• Filed: 02/27/2006
• Published: 07/06/2006
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 8,429,585 B2
• Time in Patent Office: Days
• US Class Current: 716/126
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three-dimensional semiconductor device, comprising: a circuit block located in a first module layer; and a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer.

Claims

1. A three-dimensional semiconductor device, comprising:

a configuration circuit to generate a digital signal, further comprised of;

a first element to generate a digital one signal; and

a second element to generate a digital zero signal; and

a first module layer comprising a plurality of circuit blocks, wherein at least one of the circuit blocks is controlled by the digital signal; and

a second module layer comprising one of said first or second elements positioned substantially above the first module layer.

2. The device of claim 1, wherein the configuration circuit comprises a memory element.

3. The device of claim 1, wherein the second module layer comprises one element selected from the following:

diode, transistor, capacitor, resistor, electrolyte, refractive metal, ferro-electric, carbon nano-tube, wire, thin film element, thin film resistor, thin film capacitor, thin film transistor (TFT), magnetic element, chemical element, and photo-electric element.

4. The device of claim 1, further comprising interconnect and routing circuits in a third module layer positioned above the first module layer.

5. The device of claim 1, wherein said configuration circuit is further comprised of:

said first element coupled to a voltage source at the digital one voltage level; and

said second element coupled to a voltage source at a digital zero voltage level.

6. The device of claim 1, wherein the first element comprises a programmable element coupled to a digital one supply voltage level and the second element comprises a programmable element coupled to a digital zero supply voltage level.

7. The device of claim 1, wherein one of the first or second elements of the configuration circuit is in the first module layer.

8. The device of claim 1, wherein the first module layer comprises a semiconductor substrate layer.

9. The device of claim 2, wherein the memory element further comprises one of:

fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electromagnetic elements, carbon nano-tube elements, optical elements, mask programmable elements and any other memory element.

10. The device of claim 5, wherein the first element is a thin-film P-type carrier transistor or resistor.

11. A programmable semiconductor device, wherein:

a circuit block comprises a transistor in a in a first module layer; and

a configuration circuit to control the circuit block comprising a transistor in a second module layer positioned above the first module layer.

12. The device of claim 11, wherein the configuration circuit comprises a memory element.

13. The device of claim 11, wherein the transistor in the second module layer is a thin film transistor (TFT).

14. The device of claim 11, further comprising interconnect and routing circuits in a third module layer positioned above the first module layer.

15. The device of claim 11, wherein the configuration circuit comprises a transistor in the first module layer.

16. The device of claim 13, wherein the transistor is a P-type carrier transistor further coupled to a voltage source at the digital one voltage level.

17. The device of claim 13, wherein the transistor is an N-type carrier transistor further coupled to a voltage source at the digital zero voltage level.

18. The device of claim 12, wherein the memory element further comprises:

a pull-up element coupled to a voltage source at digital one voltage level; and

a pull-down element coupled to a voltage source at a digital zero voltage level;

wherein, the configuration circuit generates a digital one or a digital zero signal level by configuring the memory element.

19. The device of claim 12, wherein the memory element further comprises one of:

fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electrochemical elements, electromagnetic elements, carbon nano-tube elements, optical elements, mask programmable elements and any other memory element.

20. A three-dimensional semiconductor device, comprising:

a circuit block located in a first module layer; and

a configuration circuit to control the circuit block further comprising a configurable element in a second module layer positioned above the first module layer.