Mechanism to emulate user-level multithreading on an OS-sequestered sequencer

• US 20060150183A1
• Filed: 12/30/2004
• Published: 07/06/2006
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Aggarwal, Anil, Zou, Xiang, Shen, John, Bigbee, Bryant, Wang, Hong, Sethi, Prashant, Chinya, Gautham N., Kaushik, Shiv, Patel, Baiju V., Hankins, Richard A., Reid, John L., Held, James Paul, Diep, Trung
• Granted Patent: US 7,810,083 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.

Claims

1. A method, comprising:

issuing one or more thread control signals to a sequencer that is sequestered from an operating system (OS);

wherein said issuing is performed by an abstraction layer in response to a user-generated instruction.

2. The method of claim 1, wherein:

said issuing is further performed by the abstraction layer in response to execution, on an OS-visible sequencer, of the user-generated instruction in an OS-visible thread.

3. The method of claim 1, wherein:

said one or more thread control signals further comprise a signal to cause the sequestered sequencer to begin executing a sequence of instructions.

4. The method of claim 3, wherein:

said one or more thread control signals further comprises a signal to cause the sequestered sequencer to begin executing a sequence of instructions at a modified instruction pointer address.

5. The method of claim 1, further comprising:

concurrently executing on a first sequencer a first instruction sequence, scheduled by the operating system, where the first instruction sequence includes the user-generated instruction;

while executing on the sequestered sequencer a second instruction sequence.

6. The method of claim 1, further comprising:

generating an execution environment for the sequestered sequencer;

wherein said generating is performed by the abstraction layer.

7. The method of claim 1, wherein said thread control signal further comprises:

a signal to interrupt execution on the sequestered sequencer.

8. The method of claim 7, wherein said thread control signal further comprises:

an interrupt signal.

9. The method of claim 1, further comprising:

performing a set of operations to cause an OS-visible sequencer to trigger execution of an event handling routine on behalf of the sequestered sequencer;

wherein said set of operations are performed by the abstraction layer.

10. The method of claim 9, wherein said set of operations further comprise:

migrating state for the sequestered sequencer to the OS-visible sequencer.

11. The method of claim 1, further comprising:

performing a set of operations to cause suspension of execution on the sequestered sequencer;

wherein said set of operations are performed by the abstraction layer in response to a ring transition on an OS-visible sequencer; and

wherein said set of operations further include issuing said one or more control signals, wherein said control signals include a signal to place the sequestered sequencer into a wait state.

12. The method of claim 11, wherein said set of operations further comprises:

tracking ring transitions on the OS-visible sequencer in a manner that is transparent to the OS.

13. The method of claim 1, further comprising:

performing a set of operations to cause resumption of execution on the sequestered sequencer;

wherein said set of operations are performed by the abstraction layer in response to completion of an exception-handling routine on an OS-visible sequencer; and

wherein said set of operations further include issuing said one or more control signals, wherein said control signals include a signal to resume execution on the sequestered sequencer.

14. The method of claim 13, wherein said set of operations further comprises:

clearing a breakpoint on the OS-visible sequencer.

39. The method of claim 12, wherein said tracking further comprises:

setting up a breakpoint for the OS-visible sequencer.

15. A system comprising:

a plurality of sequencers to concurrently execute a plurality of instruction streams;

a memory coupled to the sequencers;

an abstraction layer, coupled to the sequencers, to sequester one or more of said sequencers from an operating system;

wherein said abstraction layer is further to control execution of one or more said instruction streams on one or more of said sequestered sequencers.

16. The system of claim 15, wherein:

at least one of said plurality of sequencers is computationally asymmetric with respect to one or more of the other sequencers.

17. The system of claim 15, wherein:

said memory is a DRAM.

18. The system of claim 15, wherein:

said abstraction layer further includes a sequencer sequestration module to sequester the one or more sequencers.

19. The system of claim 15, wherein:

said abstraction layer further includes a proxy execution module to invoke operating system service for the sequestered sequencers.

20. The system of claim 15, wherein:

said abstraction layer further includes a sequencer arithmetic module to provide signaling between at least two of the plurality of sequencers.

21. The system of claim 15, wherein:

said abstraction layer further includes a transition detection module to cause at least one of the sequestered sequencers to suspend operation during a ring 0 operation of the operating system.

22. The system of claim 21, wherein:

said abstraction layer further includes a transition detection module to cause at least one of the sequestered sequencers to resume operation after a ring 0 operation of the operating system.

23. The system of claim 15, wherein:

instructions for said abstraction layer are included in said memory.

24. The system of claim 15, wherein:

said memory includes instructions to run the operating system as a guest of the abstraction layer.

25. An article comprising a machine-accessible medium having a plurality of machine accessible instructions for an abstraction layer, wherein, when the instructions are executed by a processor, the instructions provide for:

issuing one or more thread control signals to a sequencer that is sequestered from an operating system (OS).

wherein said instructions for said issuing are performed by the abstraction layer in response to a user-generated instruction.

26. The article of claim 25, wherein:

said instructions for said issuing are further performed by the abstraction layer in response to execution, on an OS-visible sequencer, of the user-generated instruction in an OS-visible thread.

27. The article of claim 25, wherein:

said one or more thread control signals further comprise a signal to cause the sequestered sequencer to begin executing a sequence of instructions.

28. The article of claim 27, wherein:

said one or more thread control signals further comprises a signal to cause the sequestered sequencer to begin executing a sequence of instructions at a modified instruction pointer address.

29. The article of claim 25, wherein said processor is further to:

concurrently execute on a first sequencer a first instruction sequence, scheduled by the operating system, where the first instruction sequence includes the user-generated instruction;

while executing on the sequestered sequencer a second instruction sequence.

30. The article of claim 25, wherein the abstraction layer instruction further include instructions that, when executed by the processor, provide for:

generating an execution environment for the sequestered sequencer.

31. The article of claim 25, wherein said thread control signal further comprises:

a signal to interrupt execution on the sequestered sequencer.

32. The article of claim 31, wherein said thread control signal further comprises:

an interrupt signal.

33. The article of claim 25, wherein the abstraction layer instructions further include instructions that, when executed by the processor, provide for:

performing a set of operations to cause an OS-visible sequencer to trigger execution of an event handling routine on behalf of the sequestered sequencer.

34. The article of claim 33, wherein said set of operations further comprise:

migrating state for the sequestered sequencer to the OS-visible sequencer.

35. The article of claim 25, wherein the abstraction layer instructions further include instructions that, when executed by the processor, provide for:

performing a set of operations to cause suspension of execution on the sequestered sequencer;

wherein said set of operations are performed by the abstraction layer in response to a ring transition on an OS-visible sequencer; and

wherein said set of operations further include issuing said one or more control signals, wherein said control signals include a signal to place the sequestered sequencer into a wait state.

36. The article of claim 35, wherein said set of operations further comprises:

setting up a breakpoint on the OS-visible sequencer.

37. The article of claim 25, wherein the abstraction layer instructions further include instructions that, when executed by the processor, provide for:

performing a set of operations to cause resumption of execution on the sequestered sequencer;

wherein said set of operations are performed by the abstraction layer in response to completion of an exception-handling routine on an OS-visible sequencer; and

wherein said set of operations further include issuing said one or more control signals, wherein said control signals include a signal to resume execution on the sequestered sequencer.

38. The article of claim 37, wherein said set of operations further comprises:

clearing a breakpoint on the OS-visible sequencer.