Semiconductor device and method of manufacturing the same

• US 20060151885A1
• Filed: 12/14/2005
• Published: 07/13/2006
• Est. Priority Date: 12/15/2004
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Keum, Dong-Yeal
• Application Number:
  US11/302,473
• Publication Number:
  US 20060151885A1
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a semiconductor device consistent with embodiments of the present invention includes forming a first insulation layer on a semiconductor substrate provided with an isolation layer and an active region; exposing a part of the active region by patterning the first insulation layer; forming a second insulation layer on the patterned first insulation layer; forming a contact hole exposing the active region and the edge portion of the first insulation layer by patterning the second insulation layer; and forming a metal layer on the second insulation layer and the exposed active region. Consequently, a junction leakage current that may be generated at the interface between the active region and the isolation layer in forming the metal contact hole can be suppressed, so the yield and reliability of devices may be enhanced.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a first insulation layer on a semiconductor substrate provided with an isolation layer and an active region;

exposing a part of the active region by patterning the first insulation layer;

forming a second insulation layer on the patterned first insulation layer;

forming a contact hole exposing the active region and the edge portion of the first insulation layer by patterning the second insulation layer; and

forming a metal layer on the second insulation layer and the exposed active region.

2. The method of claim 1, wherein an opening of the patterned first insulation layer is formed on the active region.

3. The method of claim 1, wherein a size of the contact hole is equal to or larger than that of the active region.

4. The method of claim 1, wherein the first insulation layer is formed as a silicon nitride layer.

5. The method of claim 4, wherein the silicon nitride layer is formed to have a thickness of 100-500 Å

.

6. The method of claim 1, wherein the second insulation layer is formed as a silicon oxide layer.

7. The method of claim 1, wherein a silicide layer is formed between the active region and the metal layer.

8. The method of claim 1, wherein a photomask for patterning the first insulation layer is a reverse-phase type of a photomask for patterning the active region, and a pattern of the photomask for patterning the first insulation layer is larger than a pattern of the photomask for patterning the active region.

9. The method of claim 8, wherein a developed pattern of the first insulation layer is larger than a developed pattern of the active region by 10 to 20 nm.

10. The method of claim 1, wherein the process of forming a metal layer comprises:

forming a barrier metal layer on the second insulation layer and exposed active region;

forming a metal plug in the contact hole; and

.

forming a metal line.

11. A semiconductor device, comprising:

a semiconductor substrate provided with an isolation layer and an active region;

a first insulation layer pattern formed on the semiconductor substrate and exposing a part of the active region;

a second insulation layer pattern formed on the first insulation layer pattern and having a contact hole pattern exposing the active region and the edge portion of the first insulation layer pattern; and

a metal layer formed on the second insulation layer pattern and the exposed active region.

12. The semiconductor device of claim 11, wherein an opening of the first insulation layer pattern is formed on the active region.

13. The semiconductor device of claim 11, wherein a size of the contact hole is equal to or larger than that of the active region.

14. The semiconductor device of claim 11, wherein a silicide layer is formed between the active region and the metal layer.

15. The semiconductor device of claim 11, wherein the first insulation layer is a silicon nitride layer.

16. The semiconductor device of claim 15, wherein a thickness of the silicon nitride layer is 100-500 Å

.

17. The semiconductor device of claim 11, wherein the second insulation layer is a silicon oxide layer.

18. The semiconductor device of claim 11, wherein the metal layer comprises:

a barrier metal layer formed on the second insulation layer pattern and the exposed active region;

a metal plug formed in the contact hole; and

a metal line formed on the barrier metal layer and metal plug.