Method of performing parallel test on semiconductor devices by dividing voltage supply unit

• US 20060152242A1
• Filed: 01/10/2006
• Published: 07/13/2006
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-Hoon, Ahn, Jung-Bae, Ji, Joon-Su
• Granted Patent: US 7,423,443 B2
• Time in Patent Office: Days
• US Class Current: 324/754.30
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Provided is a method of performing a parallel test on semiconductor devices, the method including coupling a power signal line to a set of at least two semiconductor devices through a switching device, performing at least one part of a parallel test on the set of semiconductor devices, and disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.

Claims

1. A method of performing a parallel test, the method comprising:

performing at least one part of a parallel test on a plurality of sets of semiconductor devices, each set including at least two semiconductor devices;

determining if at least one of the semiconductor devices of a set is defective as a result of the at least one part of the parallel test; and

disconnecting the set with at least one defective semiconductor device from at least one power signal line.

2. The method of claim 1, wherein disconnecting the set further comprises using a switching device to disconnect the set from the at least one power signal line, the switching device including a circuit module including a relay.

3. The method of claim 1, disconnecting the set further comprising disconnecting the set in response to a signal on a signal line of a performance board.

4. The method of claim 3, wherein the signal line is one selected from the group consisting of a driver signal line and an input/output signal line

5. A method of performing a parallel test, the method comprising:

coupling a power signal line to a set of at least two semiconductor devices through a switching device;

performing at least one part of a parallel test on the set of semiconductor devices; and

disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.

6. The method of claim 5, further comprising disconnecting the set of semiconductor devices from the power signal line in response to determining that at least one semiconductor device of the set is defective as a result of the at least one part of the parallel test.

7. The method of claim 5, wherein the semiconductor devices are semiconductor memory devices.

8. The method of claim 5, wherein disconnecting the semiconductor device from the set further comprises using a switching device to disconnecting the semiconductor device from the set, the switching device including a circuit module including a relay.

9. The method of claim 5, disconnecting the semiconductor device from the set further comprises disconnecting the semiconductor device from the set in response to a signal on a signal line of a performance board.

10. The method of claim 9, wherein the signal line is one of an input/output signal line and a driver signal line.

11. The method of claim 9, further comprising using the signal line to electrically test the semiconductor devices.

12. The method of claim 9, further comprising generating the signal in response to a test program used in the part of the parallel test.

13. The method of claim 12, generating the signal further comprising controlling a voltage on the signal line.

14. The method of claim 5, wherein disconnecting the semiconductor device from the set is performed after a test of the parallel test selected from the group consisting of an open/short test and a leakage test.

15. The method of claim 5, wherein performing the at least one part of the parallel test further comprises:

connecting an automatic test robot including an interface board to a performance board; and

starting the at least one part of the parallel test using the automatic test robot.

16. The method of claim 15, wherein the interface board is one selected from the group consisting of a probe card and a device under test board.

17. The method of claim 16, wherein the automatic test robot is one selected from the group consisting of a prober system and a handler.

18. An apparatus for testing semiconductor devices, comprising:

a power signal line;

a plurality of switching devices; and

a plurality of connections for testing sets of semiconductor devices, each connection coupled to the power signal line through an associated switching device, each such set of semiconductor devices including at least two semiconductor devices.

19. The apparatus of claim 18, each connection further comprising:

at least two second switching devices, each second switching device coupled between the switching device associated with the set and a connection for one of the semiconductor devices of the set.

20. The apparatus of claim 18, each connection further coupled to at least one of the group consisting of at least one driver signal line, and at least one input/output signal line.