Pulse generators with variable pulse width and sense amplifiers using the same and related methods

• US 20060152262A1
• Filed: 01/06/2006
• Published: 07/13/2006
• Est. Priority Date: 01/10/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jae-Kwan
• Application Number:
  US11/327,681
• Publication Number:
  US 20060152262A1
• Time in Patent Office: Days
• US Class Current: 327/172
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: H03K 2005/00032 Dc control of switching transistors
• CPC Class Codes: H03K 2005/00202 using current mirrors
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/153 Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant switching at zero crossing H03K17/13

Abstract

Pulse generators include a delay circuit that is responsive to an input signal. The pulse generators also include an output circuit that is configured to generate an output pulse signal in response to the output of the delay circuit. In these pulse generators, the delay circuit has a variable delay that increases proportional to increases in a power supply voltage. Sense amplifiers that include these pulse generators are also provided.

Claims

1. A pulse generator, comprising:

a delay circuit that is responsive to an input signal; and

an output circuit that is configured to generate an output pulse signal in response to an output of the delay circuit,

wherein the delay circuit has a variable delay that increases proportional to increases in a power supply voltage.

2. The pulse generator of claim 1, wherein the delay circuit comprises a first inverter that controls charging and/or discharging of at least one first capacitor.

3. The pulse generator of claim 2, wherein the delay circuit further comprises a second inverter that controls charging and/or discharging of at least one second capacitor, wherein the charge stored in the first capacitor comprises an input to the second inverter.

4. The pulse generator of claim 3, further comprising:

a reference current generating circuit that is configured to generate a reference current, wherein the delay circuit further comprises a first current mirror that is configured to generate a first mirroring current that mirrors the reference current and charges the at least one first capacitor.

5. The pulse generator of claim 5, further comprising:

a second current mirror that is configured to generate a second mirroring current that mirrors the reference current and discharges the at least one second capacitor.

6. A sense amplifier, comprising:

a variable pulse-width pulse generator that is configured to generate a pulse wave having a pulse width that increases as a power supply voltage that is supplied to the variable pulse-width pulse generator increases;

a sensing circuit that is configured to provide an output signal in response to input data and the pulse wave; and

a sense reference unit that is configured to sense the value of the input data in response to the output signal.

7. The sense amplifier of claim 6, wherein the sensing time of the sense amplifier is substantially constant for operating voltages in the range of about 1.0 volts to about 1.4 volts.

8. The sense amplifier of claim 6, further comprising:

a fixed pulse-width pulse generator that generates a second pulse wave, wherein the sensing circuit that is configured to provide an output signal in response to input data, the pulse wave and the second pulse wave.

9. The sense amplifier of claim 6, wherein the sense reference unit is configured to compare a first current that is generated in response to the output signal with a sense reference current, and is further configured to generate a second output signal based on the comparison.

10. The sense amplifier of claim 9, further comprising:

a buffer that is configured to output a third output signal that designates the value of the input data in response to the second output signal.

11. A pulse generator, comprising:

a reference current generating circuit that is configured to generate a reference current;

a charge circuit that is configured to be charged through a first mirroring current that is produced by mirroring the reference current in response to an input signal;

a discharge circuit that is configured to be discharged through a second mirroring current that is produced by mirroring the reference current in response to an output signal of the charge circuit; and

a logic circuit that is configured to generate a pulsed output signal having a pulse width that is substantially proportional to a power supply voltage in response to the input signal and an output signal of the discharge circuit.

12. The pulse generator of claim 11, wherein the pulsed output signal is in an active state when the input signal is inactive and the output signal of the discharge unit is active.

13. The pulse generator of claim 12, wherein the logic circuit comprises:

an inverter that is responsive to the output signal of the discharge unit; and

a NOR gate that is responsive to the output signal of the inverter and the input signal.

14. A pulse generator comprising:

a first current source electrically connected to a first reference voltage;

a first inverter electrically connecting the first current source and a second reference voltage, the first inverter generating a first output signal;

a second current source electrically connected to the second reference voltage to generate a second reference current;

a second inverter coupled to an output terminal of the first inverter and electrically connecting the second current source and the first reference voltage, the second inverter generating a second output signal; and

a logic circuit that is configured to generate a third output signal with a pulse width that is substantially proportional to the power supply voltage in response to the second output signal and an input signal.

15. The pulse generator of claim 14, wherein the first current source is configured to generate a first reference current, and wherein the first output signal has an inverted phase of an input signal and is generated by charging or discharging the output terminal of the first inverter via the first reference current based on the input signal.

16. The pulse generator of claim 15, wherein the second output signal has a substantially inverted phase of the first output signal and is generated by charging or discharging an output terminal of the second inverter via the second reference current based on the first output signal.

17. The pulse generator of claim 16, wherein the logic circuit outputs the third output signal as an active state when the input signal is inactive and the second output signal is active.

18. The pulse generator of claim 17, wherein, the first inverter comprises:

a first PMOS transistor having a source electrode electrically connected to the first current source, a drain electrode electrically connected to the first output terminal, and a gate electrode electrically connected to the input signal;

a first NMOS transistor having a source electrode electrically connected to the ground voltage, a drain electrode electrically connected to the first output terminal, and a gate electrode electrically connected to the input signal; and

a first capacitor coupled between the first output terminal and the ground voltage.

19. The pulse generator of claim 18, wherein the second inverter comprises:

a second PMOS transistor having a source electrode electrically connected to the power supply voltage, a drain electrode electrically connected to the second output terminal, and a gate electrode electrically connected to the first output terminal;

a second NMOS transistor having a source electrode electrically connected to the second current source, a drain electrode electrically connected to the second output terminal, and a gate electrode electrically connected to the first output terminal; and

a second capacitor coupled between the second output terminal and the ground voltage.

20. A sense amplifier, comprising:

a first pulse generator that is configured to output a first signal;

a second pulse generator that is responsive to the first signal and that is configured to output a second signal having a pulse width that is substantially proportional to the power supply voltage;

a sensing unit that is configured to receive data through a first input terminal in response to the first signal and the second signal and to output a first output signal through a first output terminal;

a sense reference unit that is configured to output a second output signal through a second output terminal in response to a comparison of the first output signal with a sense reference current; and

a buffer that is configured to output a third output signal in response to the second output signal.

21. The sense amplifier of claim 20, further comprising:

an address input buffer that is configured to receive an address input signal;

a read signal input buffer that is configured to receive a read input signal; and

an address transition delay summation circuit that is responsive to an output signal of the address input buffer and an output signal of the read signal input buffer and that is configured to output an address transition signal to the first pulse generator.

22. The sense amplifier of claim 21, wherein the second pulse generator comprises:

a reference current generating circuit that is configured to generate a reference current in response to a reference voltage and a block enable signal;

a charge circuit that is configured to be charged through a first mirroring current and generate a fourth output signal, the first mirroring current being produced by mirroring the reference current in response to the first signal;

a discharge circuit that is configured to be discharged through a second mirroring current and generate a fifth output signal, the second mirroring current being produced by mirroring the reference current in response to the fourth output signal and the reference voltage;

a logic circuit that is configured to generate the second signal in response to the first signal and the fifth output signal.