Integrated DRAM-NVRAM multi-level memory

• US 20060152963A1
• Filed: 03/03/2006
• Published: 07/13/2006
• Est. Priority Date: 08/27/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup, Forbes, Leonard
• Granted Patent: US 7,457,159 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

Claims

1. An integrated DRAM-NVRAM memory cell comprising:

a field effect transistor having a floating body portion; and

a floating plate transistor coupled to the field effect transistor through the floating body portion.

2. The memory cell of claim 1 and further including:

the field effect transistor having a drain region and a first source region located on opposite sides of the floating body; and

the floating plate transistor having a second source region and sharing the drain region with the field effect transistor, the first and second source regions each adapted to generate a depletion region that are substantially close enough together to create the floating body portion.

3. The memory cell of claim 1 wherein the field effect transistor and the floating plate transistor are vertical transistors that are fabricated in trenches and pillars formed into a substrate material.

4. The memory cell of claim 1 wherein the floating body portion stores data for a DRAM function of the cell.

5. The memory cell of claim 1 wherein the floating plate increases field effect transistor conductance by accepting excess hole charge from the floating body.

6. The memory cell of claim 1, wherein the floating plate decreases field effect transistor conductance by accepting excess electrons from the floating body.

7. The memory cell of claim 4 wherein the floating plate transistor enables the field effect transistor to store data without refresh.

8. The memory cell of claim 1 wherein the floating plate transistor is a multi-level device adapted to store a plurality of data bits.

9. The memory cell of claim 8 wherein the plurality of data bits are addressed by a first voltage level of a set of read voltage levels applied to the memory cell.

10. The memory cell of claim I wherein the floating plate transistor enhances the data storage by the field effect transistor by providing non-volatile state retention.

11. An integrated DRAM-NVRAM memory cell formed in a substrate, the memory cell comprising:

a field effect transistor having a floating body portion with a drain region and a first source region located on opposite sides of the floating body; and

a floating plate transistor coupled, through the floating body portion, to the field effect transistor and sharing the drain region with the field effect transistor, the floating plate transistor comprising;

a second source region, the first and second source regions each adapted to generate a depletion region that are substantially close enough together to create the floating body portion; and

a tunneling dielectric formed between the floating plate and the substrate.

12. The memory cell of claim 11 wherein the doped drain regions are n+regions and the substrate is a p-type conductivity.

13. The memory cell of claim 11 wherein, during operation of the memory cell, the source regions at the bottom of the first and the second trenches are adapted to generate depletion regions that substantially meet to form a floating body in the first pillar.

14. The memory cell of claim 11 and further including a vertical control gate formed adjacent to the floating plate.

15. The memory cell of claim 14 and further including a tunnel dielectric layer and a charge blocking layer formed on either side of the floating plate.

16. The memory cell of claim 15 wherein the tunnel dielectric layer and the charge blocking layer are comprised of silicon dioxide.

17. An integrated DRAM-NVRAM memory cell formed in a substrate having a pillar defined by two trenches, the memory cell comprising:

a field effect transistor having a floating body portion with a drain region in the pillar and a first source region formed under a first trench; and

a floating plate transistor coupled, through the floating body portion, to the field effect transistor and sharing the drain region with the field effect transistor, the floating plate transistor comprising;

a vertical floating plate formed adjacent to a vertical side of the pillar;

a control gate formed in the remaining trench and adjacent to the vertical floating plate;

a second source region formed under the remaining trench;

a tunneling dielectric formed between the floating plate and the pillar; and

a charge blocking layer formed between the control gate and the floating plate.

18. The memory cell of claim 17 wherein the field effect transistor comprises a vertical gate formed along an opposing side of the pillar from the vertical floating plate.

19. The memory cell of claim 17 wherein the first and second source regions are each adapted to generate a depletion region that are substantially close enough together to create the floating body portion

20. The memory cell of claim 18 wherein the vertical gate is coupled to a DRAM word line of a memory array and the control gate is coupled to a control gate word line of the memory array.