Multiple-time electrical fuse programming circuit

• US 20060152990A1
• Filed: 01/04/2005
• Published: 07/13/2006
• Est. Priority Date: 01/04/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Chien-Hua
• Granted Patent: US 7,110,313 B2
• Time in Patent Office: Days
• US Class Current: 365/225.700
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/4401 for self repair

Abstract

A multiple-time electrical fuse programming circuit is described. The circuit includes a programming counter to record the number of programmings, a blowing reference voltage generator to generate a blowing voltage reference wherein the fuse resistance after programming is determined by the blowing voltage reference, at least one self-controlled programmable fuses which includes a programmable fuse and a control circuit. The multiple-time electrical fuse programming circuit also has a fuse detection reference generator and a high voltage power source.

Claims

1. A multiple-time electrical fuse programming circuit comprising:

a programming counter;

a blowing reference voltage generator coupled to output nodes of the programming counter;

at lease one self-controlled programmable fuse coupled to a reference node of the blowing reference voltage generator; and

a fuse detection reference generator coupled to the blowing reference voltage generator.

2. The multiple-time electrical fuse programming circuit in claim 0 wherein the programming counter comprises:

a plurality of sub circuits each having an AND gate, an inverter and a fuse wherein;

the AND gate having a first input node, a second input node, and an output node;

the inverter having an input node and an output node;

the fuse having an output node coupled to the first input node of the AND gate and to the input node of the inverter and wherein the output node of the AND node is coupled to one the output nodes of the programming counter; and

wherein the plurality of sub circuits are coupled in series and wherein the output node of the inverter coupled to the second input node of the AND gate of the next sub circuit and wherein the plurality of sub circuits have an uncoupled inverter input and an uncoupled inverter output;

a fuse having an output node coupled to a last switch signal node and to the uncoupled inverter input node of the plurality of sub circuits; and

the uncoupled inverter output node of the plurality of sub circuits being coupled to a first switch signal node.

3. The multiple-time electrical fuse programming circuit in claim 0 wherein the fuse detection reference generator comprises:

a reference fuse having a first end coupled to a positive power supply node;

a first nMOS transistor having its drain coupled to the output node and its gate coupled to a fuse detection enable node;

a second nMOS transistor having its drain coupled to the source of the first transistor, its gate coupled to its drain and a bias voltage node, and its source coupled to a negative power supply node; and

the drain of the first nMOS transistor being coupled to a second end of the reference fuse.

4. The multiple-time electrical fuse programming circuit in claim 0 wherein the fuse detection reference generator comprises:

a reference fuse having a first end coupled to a negative power supply node;

a first pMOS transistor having its drain coupled to the output node and its gate coupled to a fuse detection enable node;

a second pMOS transistor having its drain coupled to the source of the first transistor, its gate coupled to its drain and a bias voltage node, and its source coupled to a positive power supply node; and

the drain of the first pMOS transistor being coupled to a second end of the reference fuse.

5. The multiple-time electrical fuse programming circuit in claim 0 wherein the blowing reference voltage generator comprises:

a blowing reference voltage node;

an MOS transistor;

a plurality of impedances coupled in series wherein the impedances having one end coupled to the MOS transistor and the other end coupled to a power supply node;

plurality of switches each having a first end coupled to one junction of impedances, a second end coupled to the blowing reference voltage node; and

a switch have a first end coupled to the drain of the transistor and a second end coupled to the blowing reference voltage node, and a switch control end coupled to the output node of the programming counter.

6. The multiple-time electrical fuse programming circuit in claim 0 wherein the MOS transistor is an nMOS transistor coupled between the plurality of impedances and the power supply node is a negative power supply node.

7. The multiple-time electrical fuse programming circuit in claim 0 wherein the MOS transistor is a pMOS transistor coupled between the plurality of impedances and the power supply node is a positive power supply node.

8. The multiple-time electrical fuse programming circuit in claim 0 wherein the impedances are selected from the group consisting of diodes, transistors and resistors.

9. The multiple-time electrical fuse programming circuit in claim 0 wherein the self-controlled programmable fuse comprises:

a programmable electrical fuse;

a fuse state detection circuit; and

a self-controlled programming circuit.

10. The multiple-time electrical fuse programming circuit in claim 0 wherein the fuse state detection circuit comprises:

a target fuse voltage generator having an output node; and

a comparator having its positive input coupled to an output node of the fuse detection reference generator and its negative input node coupled to the output node of the target fuse voltage generator.

11. The multiple-time electrical fuse programming circuit in claim 0 wherein the target fuse voltage generator comprises:

a first nMOS transistor having its drain coupled to the output node of the target fuse voltage generator and one end of the programming fuse, and its gate coupled to a fuse detection enable node; and

a second nMOS transistor having its drain coupled to the source of the first nMOS transistor, its gate coupled to a bias voltage node, and its source coupled to a negative power supply node.

12. The multiple-time electrical fuse programming circuit in claim 0 wherein the target fuse voltage generator comprises:

a first pMOS transistor having its drain coupled to the output node of the target fuse voltage generator and one end of the programming fuse, and its gate coupled to a fuse detection enable node; and

a second pMOS transistor having its drain coupled to the source of the first pMOS transistor, its gate coupled to a bias voltage node, and its source coupled to a positive voltage power supply node.

13. The multiple-time electrical fuse programming circuit in claim 0 wherein:

the fuse detection reference generator having a first current flow to a negative power supply node;

the target fuse voltage generator having a second current flow to the negative power supply node; and

the first current being smaller than the second current.

14. The multiple-time electrical fuse programming circuit in claim 0 wherein:

the fuse detection reference generator comprising a reference fuse having a first end coupled to a positive power supply node, a first nMOS transistor having its drain coupled to a second end of the reference fuse and the output node of the fuse detection reference generator, its gate coupled to a fuse detection enable node, a second nMOS transistor having its drain coupled to the source of the first transistor, its gate coupled to its drain and a bias voltage node, and its source coupled to a negative power supply node;

the target fuse voltage generator comprising a third nMOS transistor having its drain coupled to the output node, its gate coupled to the fuse detection enable node, a fourth nMOS transistor having its drain coupled to the source of the third transistor, its gate coupled to the bias voltage node, and its source coupled to the negative power supply node, and the drain of the third nMOS transistor is couple to output node of the target fuse voltage generator;

the second nMOS transistor having a first gate width-length ratio;

the fourth nMOS transistor having a second gate width-length ratio; and

the first gate width-length ratio being smaller than the second gate width-length ratio.

15. The multiple-time electrical fuse programming circuit in claim 0 wherein the self-controlled programming circuit comprises:

a programmable fuse;

a voltage comparator;

a latch; and

a gate selected from the group consisting of NAND gate and AND gate.

16. The multiple-time electrical fuse programming circuit in claim 0 wherein the latch comprises a first NAND gate and a second NAND gate.

17. The multiple-time electrical fuse programming circuit in claim 0 wherein the self-controlled programming circuit comprises:

a first node coupled to the programming fuse;

an nMOS transistor having its drain coupled to the first node and its source coupled to a negative power supply;

a comparator having its positive input node coupled to the first node, its negative input node coupled to a blowing reference voltage node;

a first NAND gate having a first input node coupled to the output node of the comparator;

a second NAND gate having a first input node coupled to the output node of the first NAND gate, a second input node coupled to a programming enable node, and an output node coupled to a second input node of the first NAND gate; and

an AND node having a first input node coupled to the output of the second NAND gate, a second input node coupled to the programming enable node, and an output node coupled to the gate of the nMOS transistor.

18. The multiple-time electrical fuse programming circuit in claim 0 wherein the self control blowing circuit comprises:

a first node coupled to the programming fuse;

a pMOS transistor having its drain coupled to the first node and its source coupled to a power supply node;

a comparator having its negative input node coupled to the first node, its positive input node coupled to a blowing reference voltage node;

a first NAND gate having a first input node coupled to the output node of the comparator;

a second NAND gate having a first input node coupled to the output node of the first NAND gate, a second input node coupled to a programming enable node, and an output node coupled to a second input node of the first NAND gate; and

an third NAND gate having a first input node coupled to the output of the second NAND gate, a second input node coupled to the programming enable node, and an output node coupled to the gate of the pMOS transistor.

19. The multiple-time electrical fuse programming circuit in claim 0 wherein the programmable electrical fuse comprises poly-silicide fuse.

20. A method of implementing a multiple-time programming fuse, the method comprises:

providing a counter;

generating a first blowing reference voltage;

programming a reference fuse using the first blowing reference voltage;

programming a first programmable fuse using the first blowing reference voltage;

incrementing the counter;

generating a second blowing reference voltage;

programming the reference fuse using the second blowing reference voltage; and

programming the first programmable fuse using the second blowing reference voltage.

21. The method of claim 0 further comprising:

generating a first state by comparing the first programmable fuse with the reference fuse after programming the reference fuse using the first blowing reference voltage;

generating a second state by comparing the multiple fuse with the reference fuse after programming the first programmable fuse using the first blowing reference voltage;

generating a third state by comparing the first programmable fuse with the reference fuse after programming the reference fuse using the second blowing reference voltage; and

generating a fourth state by comparing the programmable fuse with the reference fuse after programming the first programmable fuse using the second blowing reference voltage.

22. The method of claim 0 further comprising:

programming a plurality of second programmable fuses; and

generating states by comparing each of the second programmable fuses with the reference fuse.

23. A multiple-time electrical fuse programming circuit comprising:

means for counting the number of programming;

means for generating blowing reference voltages coupled to the means for counting the number of programming;

means for programming a reference fuse multiple times using the blowing reference voltages;

means for programming a programmable fuse multiple times using the blowing reference voltages; and

means for detecting states of the programmable fuse.

24. The multiple-time electrical fuse programming circuit of claim 23 wherein the means for counting the number of programming comprises multiple electrical fuses for recording the number of programming.

25. The multiple-time electrical fuse programming circuit of claim 23 wherein the means for generating blowing reference voltages comprises plurality of impedances for dividing a power supply voltage into the blowing reference voltages.

26. The multiple-time electrical fuse programming circuit of claim 23 wherein the means for programming a programmable fuse multiple times comprises a first comparator comparing the blowing reference voltages and a reference voltage generated by the means for programming a programmable fuse.

27. The multiple-time electrical fuse programming circuit of claim 23 wherein the means for detecting the states of the programmable fuse comprises a second comparator comparing the voltages generated by using the reference fuse and the programmable fuse.