Time-domain equalizer for discrete multi-tone based DSL systems with cyclic extension in training
First Claim
1. A method of TEQ training for VDSL-based systems that use training signals having cyclic extension comprising:
- receiving an VDSL signal at a transceiver from a VDSL channel;
performing frame alignment;
removing cyclic extension from each VDSL frame;
averaging the received signal; and
performing TEQ training.
1 Assignment
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Accused Products
Abstract
The present invention provides for a method and system to implement time-domain equalizer (TEQ) training to shorten the channel impulse response of twisted copper lines for DMT-based VDSL systems. The coefficients of TEQ are trained when training signal has cyclic extension (CE), such as specified in current VDSL standard and proposed for VDSL2. The invention effects frame alignment and removal of CE to effectively permit implementation of TEQ training for VDSL where the training signal has cyclic extension. The advantage of this new invent is that Intersymbol interference (ISI) can be reduced in the current VDSL systems and FFT (Fast Fourier Transform) can be applied in place of presently used DFT (Direct Fourier Transform) for TEQ training. Use of the present invention in effectively implementing TEQ training in systems having cyclic extension results in reduced complexity, power saving, reduced memory requirements in terms of code space, and cost savings
16 Citations
15 Claims
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1. A method of TEQ training for VDSL-based systems that use training signals having cyclic extension comprising:
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receiving an VDSL signal at a transceiver from a VDSL channel;
performing frame alignment;
removing cyclic extension from each VDSL frame;
averaging the received signal; and
performing TEQ training. - View Dependent Claims (2, 3, 4, 5)
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6. A system for performing TEQ training in a DMT-based VDSL transceiver comprising:
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an input adapted to receive an analog information signal;
an A/D converter;
circuitry adapted to perform frame alignment;
circuitry adapted to remove a cyclic extension from aligned frames prior to TEQ processing; and
circuitry adapted to perform TEQ training based on frames devoid of cyclic extension. - View Dependent Claims (7, 8, 9, 10)
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11. A VDSL chipset comprising:
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an analog front end, adapted to receive an analog VDSL signal;
an A/D converter adapted to digitize the analog signal;
a frame aligner;
a cyclic extension stripper for striping a cyclic extension from a frame;
a signal averaging circuit; and
a TEQ training circuit. - View Dependent Claims (12, 13, 14, 15)
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Specification