Time-domain equalizer for discrete multi-tone based DSL systems with cyclic extension in training

• US 20060153310A1
• Filed: 12/30/2005
• Published: 07/13/2006
• Est. Priority Date: 01/07/2005
• Status: Abandoned Application

• Current Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Tung, Tai-Lai
• Application Number:
  US11/320,918
• Publication Number:
  US 20060153310A1
• Time in Patent Office: Days
• US Class Current: 375/260
• CPC Class Codes: H04L 2025/03414 Multicarrier
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 27/2607 Cyclic extensions
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex

Abstract

The present invention provides for a method and system to implement time-domain equalizer (TEQ) training to shorten the channel impulse response of twisted copper lines for DMT-based VDSL systems. The coefficients of TEQ are trained when training signal has cyclic extension (CE), such as specified in current VDSL standard and proposed for VDSL2. The invention effects frame alignment and removal of CE to effectively permit implementation of TEQ training for VDSL where the training signal has cyclic extension. The advantage of this new invent is that Intersymbol interference (ISI) can be reduced in the current VDSL systems and FFT (Fast Fourier Transform) can be applied in place of presently used DFT (Direct Fourier Transform) for TEQ training. Use of the present invention in effectively implementing TEQ training in systems having cyclic extension results in reduced complexity, power saving, reduced memory requirements in terms of code space, and cost savings

Claims

1. A method of TEQ training for VDSL-based systems that use training signals having cyclic extension comprising:

receiving an VDSL signal at a transceiver from a VDSL channel;

performing frame alignment;

removing cyclic extension from each VDSL frame;

averaging the received signal; and

performing TEQ training.

2. The method according to claim 1, wherein an overall channel impulse response length is shorted.

3. The method according to claim 1, wherein removing cyclic extension makes a frame length of each frame a multiple of 1024 (2¹⁰) bits.

4. The method according to claim 3, wherein performing TEQ training comprises applying a fast Fourier transform (FFT) to train the TEQ.

5. The method according to claim 1, wherein neither the circulant property in the time domain nor the orthogonal property in the frequency domain are negatively affected by the step of removing cyclic extension.

6. A system for performing TEQ training in a DMT-based VDSL transceiver comprising:

an input adapted to receive an analog information signal;

an A/D converter;

circuitry adapted to perform frame alignment;

circuitry adapted to remove a cyclic extension from aligned frames prior to TEQ processing; and

circuitry adapted to perform TEQ training based on frames devoid of cyclic extension.

7. The system according to claim 6, wherein, the circuitry adapted to remove a cyclic extension from aligned frames prior to TEQ processing comprises circuitry adapted to shorten a length of each frame to a multiple of 1024 bits in length.

8. The system according to claim 7, wherein circuitry adapted to perform TEQ training based on frames devoid of cyclic extension comprises FFT circuitry adapted to perform an FFT operation.

9. The system according to claim 6, wherein the TEQ training without cyclic extension is characterized in that an overall channel impulse response length is shorted.

10. The system according to claim 6, wherein the system is adapted so that neither the circulant property in the time domain nor the orthogonal property in the frequency domain are negatively affected by the step of removing cyclic extension relative to TEQ training with cyclic extension.

11. A VDSL chipset comprising:

an analog front end, adapted to receive an analog VDSL signal;

an A/D converter adapted to digitize the analog signal;

a frame aligner;

a cyclic extension stripper for striping a cyclic extension from a frame;

a signal averaging circuit; and

a TEQ training circuit.

12. The chipset according to claim 11, wherein the cyclic extension stripper shortens a length of each frame to a multiple of 1024 bits in length for TEQ training.

13. The chipset according to claim 12, wherein the TEQ training circuit comprises a FFT circuit.

14. The chipset according to claim 11, wherein the TEQ training circuit shortens an overall VDSL channel impulse response length.

15. The chipset according to claim 11, wherein neither a circulant property in the time domain nor an orthogonal property in the frequency domain are negatively affected by the cyclic extenion stripper or the TEQ training circuit.