METHOD AND STRUCTURE FOR GENERATING OFFSET FIELDS FOR USE IN MRAM DEVICES

• US 20060154381A1
• Filed: 01/10/2005
• Published: 07/13/2006
• Est. Priority Date: 01/10/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gaidis, Michael C., Trouilloud, Philip L.
• Granted Patent: US 7,133,309 B2
• Time in Patent Office: Days
• US Class Current: 438/3
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A method for generating an offset field for a magnetic random access memory (MRAM) device includes forming a first pinned layer integrally with a wordline, and forming a second pinned layer integrally with a bitline. An MRAM cell is disposed between the wordline and the bitline, the MRAM cell including a reference layer, an antiparallel free layer and a tunnel barrier therebetween. The first pinned layer is formed with an internal magnetization in a manner so as to create a first external field generally perpendicular to a long axis of the wordline, and the second pinned layer is formed with an internal magnetization in a manner so as to create a second external field generally perpendicular to a long axis of the bitline.

Claims

1. A method for generating an offset field for a magnetic random access memory (MRAM) device, the method comprising:

forming a first pinned layer integrally with a wordline;

forming a second pinned layer integrally with a bitline;

disposing an MRAM cell between said wordline and said bitline, said MRAM cell including a reference layer, an antiparallel free layer, and a tunnel barrier therebetween;

wherein said first pinned layer is formed with an internal magnetization in a manner so as to create a first external field generally perpendicular to a long axis of said wordline, and said second pinned layer is formed with an internal magnetization in a manner so as to create a second external field generally perpendicular to a long axis of said bitline.

2. The method of claim 1, wherein said first and said second pinned layers are formed using antiferromagnets coupled to ferromagnets.

3. The method of claim 2, wherein said internal magnetization of said first pinned layer and said internal magnetization of said second pinned layer are oriented in alignment with an intrinsic axis of anisotropy of said antiparallel free layer.

4. The method of claim 3, wherein said internal magnetization of said first pinned layer and said internal magnetization of said second pinned layer are set simultaneously.

5. The method of claim 1, wherein said first and said second pinned layers are formed using intrinsically high coercivity (H_c) materials.

6. The method of claim 5, wherein said internal magnetization of said first pinned layer and said internal magnetization of said second pinned layer are oriented in alignment with an intrinsic axis of anisotropy of said antiparallel free layer.

7. The method of claim 6, wherein said internal magnetization of said first pinned layer and said internal magnetization of said second pinned layer are set simultaneously.

8. The method of claim 5, wherein said internal magnetization of said first pinned layer is oriented generally perpendicular to said long axis of said wordline, and said internal magnetization of said second pinned layer is oriented generally perpendicular to said long axis of said bitline.

9. The method of claim 8, wherein said internal magnetization of said first pinned layer and said internal magnetization of said second pinned layer are set sequentially in the absence of a thermal treatment.

10. The method of claim 1, wherein one said first and said second pinned layers is formed using antiferromagnet-coupled ferromagnet materials, and the other of said first and said second pinned layers is formed using intrinsically high coercivity (H_c) materials.

11. The method of claim 1, wherein said MRAM cell is disposed in a location between said first pinned layer and said second pinned layer such that a net offset field at said location, with respect to said first and second external fields, is aligned substantially along an intrinsic axis of anisotropy of said antiparallel free layer.

12. The method of claim 1, wherein said first pinned layer is formed at the bottom of a trench used to define said wordline.

13. The method of claim 12, wherein said second pinned layer is formed at the bottom of a trench used to define said bitline.

14. The method of claim 1, wherein said MRAM cell further comprises a 2-bit storage cell having said reference layer, said antiparallel free layer and said tunnel barrier configured to store a first bit, and a second antiparallel free layer, a second tunnel barrier, and said reference layer configured to store a second bit.

15. The method of claim 1, wherein said MRAM cell is disposed in a location between said first pinned layer and said second pinned layer such that a net offset field at said location, with respect to said first and second external fields, is aligned in a manner so as to be biased toward one of the long axes of said wordline and said bitline.

16. The method of claim 3, wherein:

said internal magnetization of said first pinned layer and said internal magnetization of said second pinned layer are set sequentially;

said internal magnetization of said first pinned layer is oriented generally perpendicular to said long axis of said wordline, and said internal magnetization of said second pinned layer is oriented generally perpendicular to said long axis of said bitline; and

said internal magnetization of said first pinned layer is set at a different temperature than for said internal magnetization of said second pinned layer, using respective antiferromagnets having different blocking temperatures.

17. The method of claim 10, wherein the antiferromagnet-coupled ferromagnet pinned layer is set by thermal treatment in a magnetic field, and the high coercivity pinned layer is set by magnetic field alone.

18. A magnetic random access memory (MRAM) device, comprising:

a first pinned layer integrally formed with a wordline;

a second pinned layer integrally formed with a bitline;

an MRAM cell disposed between said wordline and said bitline, said MRAM cell including a reference layer, an antiparallel free layer, and a tunnel barrier therebetween;

wherein said first pinned layer is formed with an internal magnetization in a manner so as to create a first external field generally perpendicular to a long axis of said wordline, and said second pinned layer is formed with an internal magnetization in a manner so as to create a second external field generally perpendicular to a long axis of said bitline.

19. The MRAM device of claim 18, wherein said first and said second pinned layers are formed using antiferromagnets coupled to ferromagnets.

20. The MRAM device of claim 19, wherein said internal magnetization of said first pinned layer and said internal magnetization of said second pinned layer are oriented in alignment with an intrinsic axis of anisotropy of said antiparallel free layer.

21. The MRAM device of claim 18, wherein said first and said second pinned layers are formed using intrinsically high coercivity (H_c) materials.

22. The MRAM device of claim 21, wherein said internal magnetization of said first pinned layer is oriented generally perpendicular to said long axis of said wordline, and said internal magnetization of said second pinned layer is oriented generally perpendicular to said long axis of said bitline.

23. The MRAM device of claim 18, wherein one said first and said second pinned layers is formed using antiferromagnetic materials, and the other of said first and said second pinned layers is formed using intrinsically high coercivity (H_c) materials.

24. The MRAM device of claim 18, wherein said MRAM cell is disposed in a location between said first pinned layer and said second pinned layer such that a net offset field at said location, with respect to said first and second external fields, is aligned substantially along an intrinsic axis of anisotropy of said antiparallel free layer.

25. The MRAM device of claim 18, wherein said first pinned layer is formed at the bottom of a trench used to define said wordline.

26. The MRAM device of claim 25, wherein said second pinned layer is formed at the bottom of a trench used to define said bitline.

27. The MRAM device of claim 18, wherein said MRAM cell further comprises a 2-bit storage cell having said reference layer, said antiparallel free layer and said tunnel barrier configured to store a first bit, and a second antiparallel free layer, a second tunnel barrier, and said reference layer configured to store a second bit.

28. The MRAM device of claim 18, wherein said MRAM cell is disposed in a location between said first pinned layer and said second pinned layer such that a net offset field at said location, with respect to said first and second external fields, is aligned in a manner so as to be biased toward one of the long axes of said wordline and said bitline.