Light emitting diode with conducting metal substrate

• US 20060154389A1
• Filed: 01/11/2005
• Published: 07/13/2006
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Foshan Nationstar Semiconductor Co., Ltd. (Foshan Nationstar Optoelectronics Company Limited)
• Original Assignee: SemiLEDs Corporation (SemiLEDs Inc)
• Inventors: Doan, Trung Tri
• Granted Patent: US 7,432,119 B2
• Time in Patent Office: Days
• US Class Current: 438/21
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/647 the elements conducting electric current to or from the semiconductor body

Abstract

Systems and methods for fabricating a light emitting diode include forming a multilayer epitaxial structure above a carrier substrate; depositing at least one metal layer above the multilayer epitaxial structure; removing the carrier substrate.

Claims

1. A method for fabricating a light emitting diode, comprising:

forming a multilayer epitaxial structure above a carrier substrate;

depositing at least one metal layer above the multilayer epitaxial structure;

removing the carrier substrate.

2. The method of claim 1, wherein the carrier substrate comprises sapphire.

3. The method of claim 1, wherein the depositing metal layer comprises electro chemical deposition.

4. The method of claim 1, wherein the depositing metal layer comprises depositing at least a metal layer followed by one or more electroless chemical depositions.

5. The method of claim 1, wherein depositing metal layer comprising applying using one of:

CVD, PECVD, PVD, ALD, MOCVD, evaporation, and plasma spray.

6. The method of claim 1, comprising depositing one or more additional metal layers above the metal layer.

7. A method for fabricating a light emitting diode, comprising:

providing a carrier substrate;

depositing a multilayer epitaxial structure;

depositing one or more metal layers above the multilayer epitaxial structure;

defining one or more mesas using etching;

forming one or more non conductive layers;

removing a portion of the non conductive layers;

depositing at least one or more metal layers; and

removing the carrier substrate.

8. The method of claim 7, wherein the carrier substrate comprises one of:

sapphire, silicon carbide, ZnO, silicon and gallium arsenide.

9. The method of claim 7, wherein the multi layer epitaxial structure comprises

a n-type GaN or AlGaN layer,

one or more quantum wells with InGaN/GaN layers, and

a p-type GaN or AlGaN layer.

10. The method of claim 7, wherein the one or more metal layers above the multi layer epitaxial structure comprises one of:

Indium Tin Oxide (ITO), Silver, Al, Cr, Pt, Ni, Au, Mo, W, a refractory metal, or a metal alloy or metal layers.

11. The method of claim 7, comprising an optional doped semiconductor layer between the multi layer epitaxial structure and the metal layers.

12. The method of claim 7, wherein a mesa is defined using a polymer and/or a hard mask for etching.

13. The method of claim 7, wherein the non-conductive layer comprises one of:

SiO2, Si3N4, a diamond like film, a non-conducting metal oxide element or a ceramic element.

14. The method of claim 7, comprising removing a portion of the non conductive layer.

15. The method of claim 7, wherein removing the portion comprises lifting off, wet or dry etching to expose a conductor layer.

16. The method of claim 15, wherein the conductor layer comprises one or more metal layers.

17. The method of claim 15, whereas the conductor layer is deposited on top of a passivation layer, wherein the passivation layer comprises one or more non-conductive layers.

18. The method of claim 7, wherein depositing one or more metal layers comprises physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), evaporation, ion beam deposition, electro chemical deposition, electroless chemical deposition, plasma spray, or ink jet deposition.

19. The method of claim 7, comprising depositing one or more metal layers using one of:

PVD, evaporation, ion beam deposition, CVD, or e-beam deposition.

20. The method of claim 19, wherein one metal layer includes one of:

chromium (Cr), Platinum (Pt), nickel (Ni), copper on tatalum nitride, molybdenum (Mo), tungsten (W) or a metal alloy.

21. The method of claim 7, comprising forming one or more of the additional metal layers by electro chemical plating or electroless chemical plating.

22. The method of claim 7, comprising forming one or more of the additional metal layers by electro chemical plating or electroless chemical plating on top of a seed layer comprises Copper, Tungsten, Gold, Nickel, Chrome, Paladium, platium or an alloy thereof.

23. The method of claim 22, wherein one of the additional metal layers comprises copper (Cu), nickel (Ni), gold (Au), aluminum (Al), or an alloy thereof.

24. The method of claim 7, comprising depositing a non conductive passivation layer.

25. The method of claim 24, wherein the passivation layer comprises one of:

non conductive metal oxide (Hafnium oxide, Titanium oxide, Tatalum oxide), Silicon dioxide, Silicon Nitride or a polymer material.

26. The method of claim 7, comprising removal a portion of the passivation layer using wet etching, chemical mechanical polishing or dry etching.

27. The method of claim 7, comprising depositing a final metal comprising one of:

copper (Cu), nickel (Ni), chromium (Cr), Platinum (Pt), zinc (Zn), their alloy.

28. The method of claim 7, comprising removing a sapphire substrate using one of:

laser, CMP, wet etching, implanting.

29. A method for fabricating a light emitting diode, comprising:

providing carrier substrate;

depositing a multilayer epitaxial structure;

defining one or more mesas using etching;

forming one or more non conductive layers;

removing a portion of the non conductive layers;

depositing one or more metal layers;

removing the carrier substrate.

30. The method of claim 29, wherein the carrier substrate comprises sapphire.

31. The method of claim 29, wherein a mesa is defined using a polymer and/or a hard mask for etching.

32. The method of claim 29, comprising depositing a non conductive passivation layer.

33. The method of claim 32, wherein the passivation layer comprises one of:

non conductive metal oxide, Silicon dioxide, Silicon Nitride, a polymer material.

34. The method of claim 29, comprising removing a portion of the passivation layer using one of:

wet etching, chemical mechanical polishing, dry etching.

35. The method of claim 29, comprising forming one or more of the additional metal layers by electro chemical plating or electroless chemical plating on top of a seed layer comprising one of:

Copper, Tungsten, Gold, Nickel, Chrome, Paladium, platinum, an alloy thereof.

36. The method of claim 35, comprising forming a seed layer on top of a mirror layer comprising Ag, Al, Ti, Cr, Pt, Pd, Ag/Pt, Ag/Pd, Ag/Cr deposited using one of:

physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), evaporation, ion beam deposition.

37. The method of claim 29, comprising depositing one or more additional metal layers above the metal layer.

38. The method of claim 29, wherein removing the carrier substrate comprising using laser lift-off (LLO) technique.

39. The method of claim 29, wherein removing the carrier substrate comprising using dry etching, Chemical removal technique or chemical mechanical removal technique.

40. A method for fabricating a light emitting diode, comprising:

providing a carrier substrate;

depositing a multilayer epitaxial structure having a p-node, a multi-quantum well (MQW), and an n-node;

depositing one or more first metal layers above the multilayer epitaxial structure that are electrically coupled to the p-node;

defining one or more mesas using etching;

forming one or more non conductive layers;

removing a portion of the non conductive layers;

depositing one or more second metal layers electrically coupled to one of the first metal layers, wherein one of the second metal layers is electrically isolated from the anode and MQW;

removing the carrier substrate.

41. A method for fabricating n-GaN up LED wafer, comprising:

providing a carrier substrate;

depositing a n-GaN portion above the carrier substrate;

depositing active layers above the n-GaN portion;

depositing a p-GaN portion above the active layers;

depositing one or more metal layers

applying a masking layer;

etching the metal, p-GaN layer, active layers and n-GaN layer,

removing the masking layer;

depositing a passivation layer;

removing portion of the passivation layer on top of the p-GaN to expose the metal,

depositing one or more metal layers

depositing a metal substrate

removing the carrier substrate to expose the n-GaN surface.

42. The method of claim 41, wherein the n-GaN up LED wafer is substantially smooth and flat.

43. The method of claim 42, wherein the n-GaN up LED wafer has a surface roughness less than 10000 angstrom.

44. The method of claim 41 wherein the carrier substrate is sapphire.

45. The method of claim 41, wherein the metal substrate is deposited using one of:

electro-chemical plating, electroless chemical plating, sputtering, chemical vapor deposition, e-beam evaporation, thermal spray.

46. The method of claim 41, wherein the metal substrate is a metal or metal alloy comprising one of Copper, nickel, aluminum, Ti, Ta, Mo, W.

47. The method of claim 41, wherein the carrier substrate is removed using one of:

laser lift-off (LLO), wet etching, chemical mechanical polishing.