Epitaxial growth method

• US 20060154451A1
• Filed: 01/05/2006
• Published: 07/13/2006
• Est. Priority Date: 01/07/2005
• Status: Active Grant

• Current Assignee: Samsung Corning Precision Materials Company Limited (Corning Incorporated)
• Original Assignee: Samsung Corning Company Limited (Corning Incorporated)
• Inventors: Park, Sung-soo
• Granted Patent: US 7,407,865 B2
• Time in Patent Office: Days
• US Class Current: 438/479
• CPC Class Codes: C30B 25/04 Pattern deposit, e.g. by using masks
• CPC Class Codes: C30B 25/183 being provided with a buffer layer, e.g. a lattice matching layer
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041

Abstract

An epitaxial growth method for forming a high-quality epitaxial growth semiconductor wafer is provided. The method includes forming a single crystalline layer on a single crystalline wafer; forming a mask layer having nano-sized dots on the single crystalline layer; forming a porous buffer layer having nano-sized pores by etching the mask layer and the surface of the single crystalline layer; annealing the porous buffer layer; and forming an epitaxial material layer on the porous buffer layer using an epitaxial growth process.

Claims

1. An epitaxial growth method comprising:

forming a single crystalline layer on a single crystalline wafer;

forming a mask layer having nano-sized dots on the single crystalline layer;

forming a porous buffer layer having nano-sized pores by etching the mask layer and the surface of the single crystalline layer;

annealing the porous buffer layer; and

forming an epitaxial material layer on the porous buffer layer using an epitaxial growth process.

2. The method according to claim 1, wherein the epitaxial material layer is formed of a Group III nitride semiconductor.

3. The method according to claim 1, wherein the single crystalline wafer is formed of one selected from the group consisting of Si, GaAs, SiC, GaN, and Al₂O₃.

4. The method according to claim 1, wherein the single crystalline wafer is formed of Al₂O₃, and the single crystalline layer and the epitaxial material layer are formed of GaN.

5. The method according to claim 4, wherein the mask layer is formed of one selected from the group consisting of Si, Al, Co, Cr, and Pt.

6. The method according to claim 1, wherein the mask layer is formed of a material having a lower etch rate than the single crystalline layer.

7. The method according to claim 1, wherein the epitaxial material layer is formed using a vapor deposition process.

8. The method according to claim 7, wherein the vapor deposition process is one selected from the group consisting of a halide or hydride vapor phase epitaxy (HVPE) process, a metal organic chemical vapor deposition (MOCVD), and a molecular beam epitaxy (MBE) process.

9. The method according to claim 1, wherein the annealing of the porous buffer layer is performed at a temperature of approximately 850°

C. or higher.

10. The method according to claim 2, wherein the single crystalline wafer is formed of Al₂O₃, and the single crystalline layer and the epitaxial material layer are formed of GaN.

11. The method according to claim 3, wherein the single crystalline wafer is formed of Al₂O₃, and the single crystalline layer and the epitaxial material layer are formed of GaN.