Reconfigurable, expandable semiconductor integrated circuit

• US 20060155969A1
• Filed: 06/08/2005
• Published: 07/13/2006
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sugiyama, Iwao, Yoda, Katsuhiro
• Granted Patent: US 7,702,884 B2
• Time in Patent Office: Days
• US Class Current: 712/226
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings, a network having reconfigurable connections and coupled to the reconfigurable circuit and to the processing circuit, and at least two interfaces each coupled to the network to provide external coupling for the network.

Claims

1. A semiconductor integrated circuit, comprising:

a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner;

a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings;

a network having reconfigurable connections and coupled to said reconfigurable circuit and to said processing circuit; and

at least two interfaces each coupled to said network to provide external coupling for said network.

2. The semiconductor integrated circuit as claimed in claim 1, further comprising, in addition to a set of said reconfigurable circuit, said processing circuit, and said network, one or more sets of another reconfigurable circuit, another processing circuit, and another network, wherein said network of said set and the networks of said one or more sets are connected in series through said interfaces, and the networks situated at opposite ends of said series are connectable to an exterior of said semiconductor integrated circuit through said interfaces.

3. The semiconductor integrated circuit as claimed in claim 1, wherein said network includes:

a plurality of signal lines; and

a selector configured to select a predetermined number of signal lines from said plurality of signal lines,

wherein only the predetermined number of signal lines selected by said selector are coupled to one of said interfaces.

4. The semiconductor integrated circuit as claimed in claim 1, further comprising:

a bus coupled to said reconfigurable circuit and said processing circuit; and

a processor coupled to said bus.

5. The semiconductor integrated circuit as claimed in claim 4, further comprising a control circuit configured to control the connections of said network, wherein said control circuit is configured to set the connections of said network in response to instruction supplied from said processor.

6. The semiconductor integrated circuit as claimed in claim 4, wherein said reconfigurable circuit is configured to define what computations are performed by said plurality of computing units in response to setting data supplied from said processor.

7. The semiconductor integrated circuit as claimed in claim 4, further comprising a system interface configured to couple said processor to an external system.

8. The semiconductor integrated circuit as claimed in claim 1, wherein said network includes a crossbar configured to interconnect between said reconfigurable circuit and said processing circuit.

9. The semiconductor integrated circuit as claimed in claim 1, wherein said parameter-defined special-purpose hardware unit includes:

a special-purpose hardware configured to perform predetermined processing; and

a setting register configured to store therein data that defines operation and processing specifications of said special-purpose hardware.

10. The semiconductor integrated circuit as claimed in claim 1, wherein said processing circuit further includes an interface configured to exchange a signal with an exterior of said semiconductor integrated circuit.