Analog counter using memory cell

• US 20060156097A1
• Filed: 11/30/2004
• Published: 07/13/2006
• Est. Priority Date: 11/30/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Camarce, Christian A., Barkley, Gerald J., Tedrow, Kerry D., Castro, Hernan A.
• Application Number:
  US10/999,598
• Publication Number:
  US 20060156097A1
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A non-volatile memory may include at least one cell that functions as an analog counter. In one embodiment, the counter may count the number of cycles experienced by the memory and provide an indication when a predetermined number of cycles have been completed. The completion of the given number of cycles may indicate a reliability issue.

Claims

1. a non-volatile memory comprising:

a counter to count the number of cycles experienced by at least a portion of said memory.

2. The memory of claim 1 wherein said memory is a flash memory.

3. The memory of claim 2 wherein said counter is a flash memory cell.

4. The memory of claim 3 wherein said counter is implemented on an otherwise unused row of said memory.

5. The memory of claim 4 including a reference cell.

6. The memory of claim 5 including a comparator to compare the threshold voltage of the reference cell to the threshold voltage of said counter.

7. The memory of claim 6 wherein said counter and said reference cell are on the same row.

8. The memory of claim 6 wherein said reference cell is a flash memory that has been preprogrammed to a particular threshold voltage.

9. The memory of claim 1 including a frequency generator to generate a pulse each time that a portion of said memory is erased.

10. The memory of claim 9 wherein said frequency generator to generate a pulse to program the counter each time a block of said memory is block erased.

11. The memory of claim 1 including a microcontroller to detect an erase cycle in said memory.

12. The memory of claim 11 wherein said microcontroller to detect a bit sequence indicative of an erase cycle.

40. The system of claim 11 wherein said microcontroller to detect a bit sequence indicative of an erase cycle.

13. A method comprising:

using a cell of a memory array to count the number of times that the memory is cycled.

14. The method of claim 13 including using a flash memory cell to count the number of times the memory is cycled.

15. The method of claim 13 including counting the number of times that a flash memory is block erased.

16. The method of claim 15 including counting the number of times that a block of flash memory is block erased using a flash memory cell associated with said block.

17. The method of claim 16 including using a cell in an unused row of flash memory to count the number of times that a block is block erased.

18. The method of claim 13 including comparing the threshold voltage of a reference cell to the threshold voltage of a cell that is programmed on each memory cycle to determine the number of memory cycles.

19. The method of claim 13 including detecting an erase command.

20. The method of claim 19 including, in response to the detection of an erase command, issuing a program pulse to a memory cell to program said memory cell.

21. The method of claim 20 including increasing the threshold voltage of the memory cell by programming the memory cell in response to the memory being cycled.

22. The method of claim 13 including preventing the erasing of a memory cell used to count the number of times that the memory is cycled.

23. An article comprising a machine accessible medium including instructions that, if executed, enable a processor-based system to:

count the number of times that a memory is cycled.

24. The article of claim 23 further including instructions that, if executed, enable a processor-based system to count the number of times that a flash memory is block erased.

25. The article of claim 23 further including instructions that, if executed, enable the threshold voltage of a reference cell to be compared to the threshold voltage of a cell that is programmed on each memory cycle to determine the number of memory cycles.

26. The article of claim 23 further including instructions that, if executed, enable the processor-based system to detect an erase command.

27. The article of claim 26 further including instructions that, if executed, enable the processor-based system to issue a program pulse to a memory cell to program said memory cell in response to the detection of an erase command.

28. The article of claim 23 further including instructions that, if executed, prevent the erasing of a memory cell used to count the number of times that a memory is cycled.

29. A system comprising:

a processor;

a wireless interface coupled to said processor;

a non-volatile memory coupled to said processor; and

a counter to count the number of cycles experienced by at least a portion of said memory.

30. The system of claim 29 wherein said memory is a flash memory.

31. The system of claim 30 wherein said counter is a flash memory cell.

32. The system of claim 31 wherein said counter is implemented on an otherwise unused row of said memory.

33. The system of claim 32 including a reference cell.

34. The system of claim 33 including a comparator to compare the threshold voltage of the reference cell to the threshold voltage of said counter.

35. The system of claim 34 wherein said counter and said reference cell are on the same row.

36. The system of claim 34 wherein said reference cell is a flash memory that has been preprogrammed to a particular threshold voltage.

37. The system of claim 29 including a frequency generator to generate a pulse each time that a portion of said memory is erased.

38. The system of claim 37 wherein said frequency generator to generate a pulse to program the counter each time a block of said memory is block erased.

39. The system of claim 29 including a microcontroller to detect an erase cycle in said memory.