Addressing error and address detection systems and methods

• US 20060156154A1
• Filed: 12/22/2004
• Published: 07/13/2006
• Est. Priority Date: 12/22/2004
• Status: Active Grant

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Inventors: Driediger, Steve
• Granted Patent: US 7,418,636 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G11C 29/024 in decoders

Abstract

Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether the target address output on the address path is detected at the memory. Address detection at the memory involves storing the target address, monitoring the address path for the target address, and providing an address detection indication based on whether the target address is detected on the address path. The address detection indication may be provided, for example, by setting a flag in a data structure which is stored in the memory.

Claims

1. An addressing error detection system for detecting addressing errors in an electronic system, the addressing error detection system comprising:

an interface to an address path and a data path which support communication with an addressable memory in the electronic system;

a processor coupled to the interface and configured to write a target address to the memory, to output the target address on the address path through the interface, and to detect an addressing error by determining whether the target address output on the address path is detected at the memory.

2. The addressing error detection system of claim 1, wherein the processor is further configured to repeat operations of writing, outputting, and determining for each of a plurality of target addresses.

3. The addressing error detection system of claim 1, wherein the memory comprises a memory of an electronic device in the electronic system, the electronic device being configured to monitor the address path for the target address and to set a flag in the memory responsive to detecting the target address on the address path, and wherein the processor is configured to determine whether the target address output on the address path is detected at the memory by determining whether the flag has been set in the memory.

4. The addressing error detection system of claim 1, wherein:

the processor is further configured to write a tag value to the memory;

the tag value is transformed at the memory in a predetermined manner during storage to or retrieval from the memory; and

the processor is further configured to retrieve the tag value from the memory, and to detect an addressing error by determining whether the tag value has been transformed in the predetermined manner.

5. The addressing error detection system of claim 1, further comprising:

a further interface to an alternate communication path which supports communication with the memory,

wherein the processor is coupled to the further interface and configured to write the target address to the memory through the further interface and to determine whether the target address output on the address path is detected at the memory by accessing the memory through the further interface.

6. A method of detecting addressing errors in an electronic system, the method comprising:

writing a target address to an addressable memory in the electronic system;

outputting the target address on an address path through which the memory is addressable; and

detecting an addressing error by determining whether the target address output on the address path is detected at the memory.

7. The method of claim 6, further comprising:

repeating the writing, outputting, and determining for each of a plurality of target addresses.

8. The method of claim 6, wherein the memory comprises a memory of an electronic device in the electronic system, the electronic device being configured to monitor the address path for the target address and to set a flag in the memory responsive to detecting the target address on the address path, and wherein determining comprises determining whether the flag has been set in the memory.

9. The method of claim 6, further comprising:

writing a tag value to the memory, the tag value being transformed at the memory in a predetermined manner during storage to or retrieval from the memory;

retrieving the tag value from the memory; and

detecting an addressing error by determining whether the tag value has been transformed in the predetermined manner.

10. The method of claim 6, wherein:

the electronic system comprises a communication path comprising the address path and an alternate communication path which supports communication with the memory;

writing comprises writing the target address to the memory through the alternate communication path; and

determining comprises accessing the memory through the alternate communication path.

11. An address detection system for detecting addresses in an electronic system, the address detection system comprising:

an interface for receiving a target address and an address of an addressable memory location;

a memory device comprising the addressable memory location and coupled to the interface for storing the target address in the addressable memory location; and

an address match detector coupled to the memory and to an address path through which the memory location is addressable and configured to monitor the address path for the target address and to provide an address detection indication based on whether the target address is detected on the address path.

12. The address detection system of claim 11, wherein the address match detector is configured to provide the address detection indication by setting a flag in the memory location where the target address is detected on the address path.

13. The address detection system of claim 12, wherein the target address and the address are received from a processor, and wherein the processor is configured to output the target address on the address path, and to subsequently access the flag to determine whether the target address was detected by the address match detector.

14. The address detection system of claim 11, wherein the interface further receives tag value for storage in the addressable memory location, and wherein the memory device transforms the tag value in a predetermined manner during storage to or retrieval from the addressable memory location.

15. The address detection system of claim 11, wherein the interface comprises an interface to an alternate communication path which supports communication with the memory, the alternate communication path being distinct from the address path.

16. An electronic system comprising:

a plurality of electronic devices, each comprising the address detection system of claim 11;

and

a processor configured to send to each of the plurality of electronic devices a target address and an address of an addressable memory location in a memory of the electronic device, to output each target address on the address path, and to determine, based on the indication provided by the address match detector of each of the plurality of electronic devices, whether each target address output on the address path is detected by the electronic device to which it was sent.

17. A method of detecting addresses in an electronic system, the method comprising:

receiving a target address and an address of an addressable memory location;

storing the target address in the addressable memory location;

monitoring an address path through which the memory location is addressable; and

providing an address detection indication based on whether the target address is detected on the address path.

18. The method of claim 17, wherein providing comprises setting a flag in the memory location where the target address is detected on the address path.

19. The method of claim 18, wherein receiving comprises receiving the target address and the address from a processor, further comprising, at the processor:

outputting the target address on the address path; and

accessing the flag to determine whether the target address was detected on the address path.

20. The method of claim 17, further comprising:

receiving a tag value for storage in the addressable memory location; and

transforming the tag value in a predetermined manner during storage to or retrieval from the addressable memory location.

21. A machine-readable medium storing a data structure comprising:

an address field storing a target address; and

a flag field storing a flag which indicates whether the target address has been detected on an address path by which medium is addressable.

22. The medium of claim 21, wherein the data structure further comprises:

a tag field storing a tag value which is transformed in a predetermined manner upon storage to or retrieval from the tag field.