System and method for managing processor execution in a multiprocessor system

• US 20060156291A1
• Filed: 01/12/2005
• Published: 07/13/2006
• Est. Priority Date: 01/12/2005
• Status: Abandoned Application

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Nijhawan, Vijay, Mahmoud, Samer El-Haj
• Application Number:
  US11/034,381
• Publication Number:
  US 20060156291A1
• Time in Patent Office: Days
• US Class Current: 717/129
• CPC Class Codes: G06F 2209/522 Manager
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A multiprocessor information handling system and method for operation is disclosed in which each of the processors of the system executes a software program according to a controlled execution scheme. A bootstrap processor sets a grouping of processor-specific flags to identify whether each respective processor is enabled to execute the software program. If the processor is enabled to execute the software program, the processor executes the software program and resets the processor-specific flag so that the software program will not be executed a second time by the processor or a logical processor of the processor.

Claims

1. A method for managing execution of software code by the processors of a multiprocessor computer system, comprising:

setting a first flag to identify whether the computer system is in a managed execution mode for the execution of the software code;

identifying at each processor whether the computer system is in a managed execution mode;

if the processor is in a managed execution mode, identifying at each processor whether a second, processor-specific flag has been set to limit execution of the software code by the processor;

executing the software code by the processor if the processor-specific flag indicates that the software code has not been previously executed by the processor.

2. The method for managing execution of software code by the processors of a multiprocessor computer system of claim 1, wherein the step of executing the software code by the processor, comprises the steps of:

determining if a semaphore is available to the processor;

acquiring the semaphore if the semaphore is available to the processor; and

executing the software code by the processor if the processor-specific flag indicates that the software code has not been previously executed by the processor.

3. The method for managing execution of software code by the processors of a multiprocessor computer system of claim 1, wherein the first flag and each processor specific flag comprise a bitmapped set of bits that are stored in a non-volatile memory location accessible to each of the processor of the computer system.

4. The method for managing execution of software code by the processors of a multiprocessor computer system of claim 1, wherein the first flag and each processor specific flag comprise a bitmapped set of bits that are stored in a non-volatile memory location in a bridge device of the computer system.

5. The method for managing execution of software code by the processors of a multiprocessor computer system of claim 1, wherein the step of identifying at each processor whether the computer system is in a managed execution mode comprises the step of identifying whether the first flag is set to identify that the computer system is in a managed execution mode.

6. The method for managing execution of software code by the processors of a multiprocessor computer system of claim 1, wherein one of the processors of the computer system is the bootstrap processor of the computer system.

7. The method for managing execution of software code by the processors of a multiprocessor computer system of claim 1, wherein one of the processor of the computer system is a bootstrap processor and wherein the bootstrap processor sets the first flag and each processor-specific second flag.

8. A information handling system, comprising

a bootstrap processor;

an application processor, wherein the bootstrap processor is communicatively coupled to the bootstrap processor via a bus;

wherein the bootstrap processor is operable to set a first flag to indicate whether the bootstrap processor and the application processor will execute a piece of software in a managed execution mode;

wherein the bootstrap processor and the application processor are operable to consult the first flag to determine if each will execute the piece of software in a managed execution mode;

wherein each of the bootstrap processor and the application processor are operable to execute the software code if the (a) first flag identifies that the processor will execute the software in a managed execution mode; and

(b) a second flag indicates that the piece of software has not been executed by the processor.

9. The information handling system of claim 8,

wherein each of the bootstrap processor and the application processor include multiple logical processors;

and

wherein each logical processor is operable to execute the piece of software.

10. The information handling system of claim 8,

wherein each of the bootstrap processor and the application processor include multiple logical processors;

wherein each logical processor is operable to execute the piece of software; and

wherein each logical processor is operable to reset the second flag to indicate that the piece of software has been executed by the processor and to prevent subsequent execution by other logical processors of the processor.

11. The information handling system of claim 8, wherein the first flag and the second flag associated with each of the bootstrap processor and the application processor comprise a bit set that is saved to nonvolatile memory within the information handling system.

12. The information handling system of claim 8, wherein the first flag and the second flag associated with each of the bootstrap processor and the application processor comprise a bit set that is saved to a nonvolatile memory within a bridge device that is coupled to the host bus of the computer system.

13. The information handling system of claim 8,

wherein each of the bootstrap processor and the application processor include multiple logical processors;

wherein each logical processor is operable to execute the piece of software;

wherein each logical processor is operable to reset the second flag to indicate that the piece of software has been executed by the processor and to prevent subsequent execution by other logical processors of the processor; and

wherein the first flag and the second flag associated with each of the bootstrap processor and the application processor comprise a bit set that is saved to a nonvolatile memory within a bridge device that is coupled to the host bus of the computer system.

14. The information handling system of claim 8, wherein each of the bootstrap processor and the application processor is unable to execute the piece of software unless the bootstrap processor or the application processor controls a semaphore accessible to each of the bootstrap processor and the application processor.

15. The information handling system of claim 8,

wherein each of the bootstrap processor and the application processor is unable to execute the piece of software unless the bootstrap processor or the application processor controls a semaphore accessible to each of the bootstrap processor and the application processor;

wherein each of the bootstrap processor and the application processor include multiple logical processors;

wherein each logical processor is operable to execute the piece of software;

wherein each logical processor is operable to reset the second flag to indicate that the piece of software has been executed by the processor and to prevent subsequent execution by other logical processors of the processor; and

wherein the first flag and the second flag associated with each of the bootstrap processor and the application processor comprise a bit set that is saved to nonvolatile memory within the information handling system.

16. A method for managing the execution of a software program in a multiprocessor computer system, comprising the steps of:

setting a execution control signal, wherein the execution control signal is set by a bootstrap processor of the computer system and identifies if the processors of the computer system will execute the software program in a controlled execution mode;

setting an execution enable signal for each logical processor of the computer system;

executing the software at each of the logical processors, wherein any logical processor will only execute the software program if (a) the execution control signal is set to indicate that the logical processor will execute the software programmed in a controlled execution mode, and (b) the execution enable signal associated with the logical processor indicates that the software program has not been executed with respect to the processor.

17. The method for managing the execution of a software program in a multiprocessor computer system of claim 16, wherein the step of resetting the execution enable signal associated with a logical processor following the execution of the software program.

18. The method for managing the execution of a software program in a multiprocessor computer system of claim 16, wherein the software program is executed in at least one of the processors by at least one of the logical processors of the processor.

19. The method for managing the execution of a software program in a multiprocessor computer system of claim 16, wherein the execution control signal and the execution enable signal for each logical processor are stored in a non-volatile memory location accessible by each of the processors of the computer system.

20. The method for managing the execution of a software program in a multiprocessor computer system of claim 16, wherein the execution control signal and the execution enable signal for each logical processor are stored in a non-volatile memory in a bridge device of the computer system.