Structure and method for biasing phase change memory array for reliable writing

• US 20060157679A1
• Filed: 01/19/2005
• Published: 07/20/2006
• Est. Priority Date: 01/19/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Granted Patent: US 7,307,268 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Abstract

A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Claims

1. In an integrated circuit comprising an array of memory cells each comprising a diode and a memory material that is reversibly switchable from one state to another by thermal activation, and each connected in series between a word line and a bit line, a method of writing at least one selected memory cell while not disturbing unselected memory cells comprising:

controlling voltages on word lines and bit lines not connected to the at least one selected memory cell;

controlling voltage on one of a word line and a bit line connected to the at least one selected memory cell; and

controlling current on another of the word line and bit line connected to the at least one selected memory cell such that the current produces the thermal activation.

2. The method of claim 1, wherein the memory material comprises a phase change material.

3. The method of claim 1, wherein current and voltage on the word line and bit line connected to the at least one selected memory cell are controlled such that voltage drop across the selected at least one memory cell is larger than voltage drops across unselected memory cells.

4. The method of claim 1, wherein the voltages on bit lines not connected to the at least one selected memory cell differ from voltages on word lines connected to the at least one selected memory cell by an amount less than a threshold voltage of the diode.

5. The method of claim 1, wherein the voltages on word lines not connected to the at least one selected memory cell differ from voltages on bit lines connected to the at least one selected memory cell by an amount less than a threshold voltage of the diode.

6. The method of claim 1, wherein:

controlling voltage on one of the word line and bit line connected to the at least one selected memory cell comprises controlling voltage on the word line connected to the selected memory cell, and

controlling current on another of the word line and bit line connected to the at least one selected memory cell comprises controlling current on the bit line connected to the at least one selected memory cell.

7. The method of claim 6, wherein the voltage on the word line connected to the at least one selected memory cell is brought to a lowest voltage applied to the array of memory cells and the current on the bit line connected to the at least one selected memory cell is pulled to a value selected by a current mirror.

8. The method of claim 6, wherein the voltage on the word line connected to the at least one selected memory cell is brought to a voltage higher than the voltages on bit lines not connected to the at least one selected memory cell, and the bit line connected to the at least one selected memory cell is pulled to a value selected by a current mirror.

9. The method of claim 6, wherein the current is supplied from a voltage source having a voltage higher than the voltages on the word lines not connected to the at least one selected memory cell.

10. The method of claim 1, wherein controlling voltage on one of the word line and bit line connected to the selected memory cell comprises controlling voltage on the bit line connected to the selected memory cell, and the controlling current on another of the word line and bit line connected to the selected memory cell comprises controlling current on the word line connected to the at least one selected memory cell.

11. The method of claim 1, wherein writing at least one selected memory cell comprises writing a plurality of selected memory cells.

12. The method of claim 11, wherein:

controlling voltage on one of a word line and a bit line connected to the at least one selected memory cell comprises controlling voltage on the word line, and

controlling current on another of the word line and bit line connected to the at least one selected memory cell comprises controlling current on a first bit line connected to a first memory cell and controlling current on a second bit line connected to a second memory cell.

13. The method of claim 12, wherein

controlling current on a first bit line connected to a first memory cell comprises connecting a first current mirror to the first memory cell, and

controlling current on a second bit line connected to a second memory cell comprises connecting a second current mirror to the second memory cell.

14. The method of claim 13, wherein the first current mirror and second current mirror cause the phase change material in the first and second memory cells to assume different states.

15. The method of claim 13, wherein the first current mirror supplies a current at least 50% greater than a current supplied by the second current mirror.

16. The method of claim 13, wherein the first current mirror supplies current to the first memory cell for a period at least twice as long as a period during which the second current mirror supplies current to the second memory cell.

17. The method of claim 11, wherein writing a plurality of selected memory cells comprises writing memory cells connected to a first plurality of bit lines while a second plurality of bit lines is being biased to an unselected bias voltage.

18. The method of claim 17, wherein writing memory cells connected to a first plurality of bit lines comprises simultaneously writing a portion of a word selected by a word line while holding other memory cells selected by the word line to an unselected bias voltage.

19. The method of claim 1, wherein the memory cells are formed in a plurality of layers above a substrate.

20. The method of claim 1, where memory cells on more than one layer of the plurality of layers are written simultaneously.

21. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure within the integrated circuit for writing to the memory cells comprising:

a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;

a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and

a bit line driver receiving the controlled current and an unselected bit line voltage, the bit line driver selecting between providing to a bit line the controlled current and the unselected bit line voltage in response to a driver control signal, the bit line providing the controlled current to at least one of the memory cells comprising phase change memory elements.

22. The structure of claim 21, wherein the driver control signal is an output signal from a decoder.

23. The structure of claim 21, further including a deselection control device which causes the bit line driver to apply the unselected bit line voltage when the pulse width control transistor is off.

24. The structure of claim 23, wherein when the pulse width control transistor is off, the deselection control device connects the unselected bit line voltage to a terminal for providing the controlled current to the bit line driver.

25. The structure of claim 21, further including a second bit line driver receiving a second controlled current from a second slave arm of a second current mirror as controlled by a second pulse width control transistor in series with the second slave arm, the second bit line driver being controlled by the driver control signal.

26. The structure of claim 25, wherein the second bit line driver provides the second controlled current to a second bit line as the bit line driver provides the unselected bit line voltage to the bit line.

27. The structure of claim 25, wherein the second bit line driver provides the second controlled current to a second bit line as the bit line driver provides the controlled current to the bit line.

28. The structure of claim 27, wherein the second controlled current is substantially different from the controlled current.

29. The structure of claim 25, wherein the bit line and the second bit line are in different memory cell layers.

30. The structure of claim 21, further comprising a pulse width controller for controlling the pulse width.

31. The structure of claim 30, wherein the pulse width controller causes the pulse width to be about 200 nanoseconds for resetting a memory cell and between 500 and 1000 nanoseconds for setting a memory cell.

32. The structure of claim 21, wherein the control current causes the controlled current to be about 20 microamps for setting a memory cell, and about 100 microamps for resetting a memory cell.

33. The structure of claim 21, wherein each of the memory cells comprising phase change memory elements comprises a diode in series with a phase change memory element.

34. The structure of claim 21, wherein the memory cells are formed in a plurality of layers above a substrate.

35. In an integrated circuit comprising memory cells comprising phase change memory elements, a structure for fast successive writing to the memory cells comprising:

a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;

a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width;

a deselection control device for providing an unselected voltage to the output terminal at times not within the pulse width; and

structure for connecting the output terminal to terminals of a plurality of the memory cells.

36. The structure of claim 35, wherein the structure for connecting the output terminal to terminals of a plurality of the memory cells comprises a plurality of drivers, the plurality of drivers each connecting the output terminal to a bit line in response to a different bit line decoder output signal.

37. The structure of claim 35, wherein the structure for connecting the output terminal to terminals of a plurality of the memory cells comprises a plurality of drivers, the plurality of drivers each connecting the output terminal to a word line in response to a different word line decoder output signal.

38. The structure of claim 35, wherein the plurality of memory cells are formed in a plurality of memory cell layers above a substrate.

39. The structure of claim 35, wherein the memory cells comprising phase change memory elements each comprise a phase change memory element in series with a diode.

40. In an integrated circuit comprising an array of memory cells each comprising a phase change material, a structure for simultaneously writing a plurality of bits to the array of memory cells comprising:

a plurality of pulse control structures acting simultaneously, each of the pulse control structures able to operate in three modes,

a first mode in which the pulse control structure provides a high current of short duration to one of the memory cells,

a second mode in which the pulse control structure provides a current lower than the high current and of longer duration than the short duration to one of the memory cells, and

a third mode in which the pulse control structure provides no current to one of the memory cells.

41. The structure of claim 40, wherein the plurality of bits are in memory cells in a plurality of memory layers of the memory array.

42. The structure of claim 40, wherein the current lower than the high current is less than 60% of the high current.

43. The structure of claim 42, wherein the current lower than the high current is less than 50% of the high current.

44. The structure of claim 40, wherein the longer duration is more than twice the short duration.

45. The structure of claim 44, wherein the longer duration is about five times as long as the short duration.

46. The structure of claim 40, wherein each of the plurality of pulse control structures provides an output signal received by a plurality of driver circuits, each of the driver circuits selecting the output signal if selected by a decoder signal selecting the driver circuit.

47. The structure of claim 40, wherein the plurality of pulse control structures acting simultaneously each provides a current selectable by a plurality of bit line driver circuits, only one of which selects the current at one time.

48. The structure of claim 40, wherein the pulse control structures acting simultaneously provide current to a plurality of bit line driver circuits commonly controlled by a bit line decoder output signal.

49. The structure of claim 40, wherein each of the memory cells each comprising a phase change material also further comprises a diode in series with the phase change material.

50. An integrated circuit structure comprising:

a structure for writing to memory cells comprising phase change memory elements, the structure for writing comprising;

a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current;

a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width; and

a plurality of memory cells for storing integrated circuit control information, each comprising a series combination of;

a phase change material and an antifuse.

51. The integrated circuit structure of claim 50, wherein the pulse width control transistor in series with the current mirror is in series with the slave arm of the current mirror.

52. The integrated circuit structure of claim 50, wherein the memory cells are formed in a plurality of memory cell layers above a substrate.

53. The integrated circuit structure of claim 50, wherein the series combination of a phase change material and an antifuse comprises a series combination of a phase change material, an antifuse, and a diode.

54. In an integrated circuit array of memory cells each containing a phase change memory element in series with a diode, the memory cells positioned at intersections with bit lines extending in a first direction and word lines extending in a second direction, a method for reading at least one selected memory cell in the array comprising:

bringing selected bit lines and unselected word lines to a first voltage;

bringing unselected bit lines and selected word lines to a second voltage, the second voltage being

different from the first voltage by an amount sufficient to detect a state of at least one selected memory cell; and

greater or less than the first voltage such that the diode of the at least one selected memory cell has its anode at a higher voltage than its cathode, and the diodes not connected to the selected word line or the selected bit line have their cathodes at a higher voltage than their anodes; and

sensing current flowing through the selected memory cell.

55. The method of claim 54, wherein half-selected memory cells in the array of memory cells experience no voltage drop.

56. The method of claim 54, wherein the selected at least one memory cell is a plurality of selected memory cells located on multiple memory cell layers of an integrated circuit in which the memory array is formed.

57. The method of claim 56, wherein at least some of the selected memory cells on multiple memory cell layers are read simultaneously.

58. The method of claim 54, wherein bringing selected bit lines and unselected word lines to a first voltage comprises connecting the unselected word lines to one input of an operational amplifier and connecting the selected bit lines to another input of the operational amplifier.

59. The method of claim 54, wherein the memory cells are formed in a plurality of memory cell layers above a substrate.

60. In an integrated circuit array of memory cells each comprising a phase change material and a diode connected in series between a word line and a bit line, a method of writing successive memory cells while not disturbing previously selected memory cells comprising:

pulling word lines connected to the previously selected memory cells to an unselected voltage;

pulling bit lines connected to the previously selected memory cells to an unselected voltage;

pulling successive word lines to a selected word line level; and

applying a selected current for a selected pulse width to successive bit lines to cause a selected values to be written into selected memory cells each comprising a phase change material and a diode.

61. An integrated circuit memory comprising:

a plurality of memory cells layers, each memory cell layer comprising;

a layer of bit lines extending in a first direction;

a layer of word lines extending in a second direction; and

a layer of phase change memory cells, each phase change memory cell extending between one of the bit lines and one of the word lines; and

structure for controlling current and pulse width for writing the phase change memory cells comprising;

a current mirror having a master arm and a slave arm, the master arm receiving a control current and the slave arm providing a controlled current; and

a pulse width control transistor in series with the current mirror, the pulse width control transistor having a control terminal for turning on the pulse width control transistor for one pulse width and supplying the controlled current to an output terminal during the pulse width.

62. The integrated circuit memory of claim 61, wherein the output terminal supplies a bit line bias applied by a bit line decoder to a bit line of a memory array.

63. The integrated circuit memory of claim 61, wherein the output terminal supplies a word line bias applied by a word line decoder to a word line of a memory array.

64. The integrated circuit memory of claim 61, wherein the controlled current and the pulse width are selected to cause a memory cell to move to a selected state.

65. The integrated circuit memory of claim 64, wherein the selected state is an amorphous state representing a reset state or a logic 0.

66. The integrated circuit memory of claim 64, wherein the selected state is a crystalline state representing a set state or a logic 1.

67. The integrated circuit memory of claim 61, wherein each of the phase change memory cells also comprises a diode.