Non-planar MOS structure with a strained channel region

• US 20060157687A1
• Filed: 01/18/2005
• Published: 07/20/2006
• Est. Priority Date: 01/18/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jin, Been-Yih, Doyle, Brian S., Datta, Suman, Chau, Robert
• Granted Patent: US 7,193,279 B2
• Time in Patent Office: Days
• US Class Current: 257/19
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

Claims

1. A non-planar transistor comprising:

a silicon germanium body formed on a substrate and electrically isolated from the substrate;

a strained silicon formed on the silicon germanium body;

a gate dielectric formed on the strained silicon;

a gate formed on the gate dielectric; and

a source and a drain formed in the strained silicon.

2. The non-planar transistor of claim 1, the silicon germanium body comprising a germanium concentration of approximately between 5% and 80%.

3. The non-planar transistor of claim 2, the silicon germanium body comprising a germanium concentration of approximately 15%.

4. The non-planar transistor of claim 1, the gate dielectric comprising a material selected from the group consisting of silicon dioxide, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantanate, and lead zinc niobate.

5. The non-planar transistor of claim 1, the gate comprising a material selected from the group consisting of polysilicon, metal, and a combination thereof.

6. The non-planar transistor of claim 1 wherein the silicon germanium body has a substantially rectangular cross section and the strained silicon is formed on a top and both sidewalls of the silicon germanium body.

7. The non-planar transistor of claim 1 wherein the silicon germanium body has a substantially trapezoidal cross section and the strained silicon is formed on a top and both sidewalls of the silicon germanium body.

8. The non-planar transistor of claim 1 wherein the strained silicon has a thickness of approximately between 2 nanometers and 10 nanometers.

9. The non-planar transistor of claim 8 wherein the strained silicon has a thickness of approximately between 4 nanometers and 5 nanometers.

10. A tri-gate transistor comprising:

a silicon germanium fin formed on an insulator, the silicon germanium fin including a top surface and two sidewall surfaces;

a strained silicon film formed on the top surface and two sidewall surfaces of the silicon germanium fin;

a gate dielectric formed on the strained silicon film;

a gate formed on the gate dielectric wherein the gate extends over the top surface of the silicon germanium fin; and

a source and a drain formed in the strained silicon film.

11. The tri-gate transistor of claim 10, the silicon germanium fin comprising a germanium concentration of approximately between 5% and 80%.

12. The tri-gate transistor of claim 11, the silicon germanium fin comprising a germanium concentration of approximately 15%.

13. The tri-gate transistor of claim 10 wherein the strained silicon film has a thickness of approximately between 2 nanometers and 10 nanometers.

14. The tri-gate transistor of claim 13 wherein the strained silicon film has a thickness of approximately between 4 nanometers and 5 nanometers.

15. A method comprising:

forming silicon germanium on a silicon on insulator substrate;

annealing the silicon germanium to relax the silicon germanium;

forming a fin in the relaxed silicon germanium, the fin including a top surface and two sidewall surfaces; and

forming strained silicon on the top surface and two sidewall surfaces of the fin.

16. The method of claim 15, annealing the silicon germanium further comprising diffusing germanium into the silicon of the silicon on insulator substrate.

17. The method of claim 16 further comprising:

forming a gate dielectric on the strained silicon film, the gate dielectric material selected from the group consisting of silicon dioxide, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantanate, and lead zinc niobate.

18. The method of claim 17 further comprising:

forming a gate on the gate dielectric, the gate material selected from the group consisting of polysilicon, metal, and a combination thereof.

19. The method of claim 18 further comprising:

doping the strained silicon to form a source and a drain.

20. An apparatus comprising:

a tri-gate transistor including a strained silicon channel region.

21. The apparatus of claim 20 wherein the strained silicon channel region has a thickness of

approximately between 2 nanometers and 10 nanometers.

22. The apparatus of claim 21 wherein the strained silicon channel region has a thickness of approximately between 4 nanometers and 5 nanometers.