Semiconductor device and method of manufacturing semiconductor device

• US 20060157734A1
• Filed: 01/12/2006
• Published: 07/20/2006
• Est. Priority Date: 01/17/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nishida, Tomoya, Nakamura, Mitsuhiro, Onodera, Koji
• Granted Patent: US 7,579,634 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7785 with more than one donor layer

Abstract

A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.

Claims

1. A semiconductor device comprising:

a field effect transistor utilizing a heterojunction, said field effect transistor formed in a device formation region sectioned by a device separation region on a semiconductor substrate, wherein said device separation region includes a layer with a conductive impurity introduced therein; and

an electrode to which a positive voltage can be applied is formed on a surface of at least a part of said device separation region in the periphery of said field effect transistor.

2. The semiconductor device as set forth in claim 1, wherein a layer device separated by implantation of an ion in a concentration higher than that in the device separation region is formed in the part of the device separation region where said electrode is formed.

3. The semiconductor device as set forth in claim 1, wherein an active region is formed in the part of the device separation region, where said electrode is formed.

4. The semiconductor device as set forth in claim 3, wherein the layer device is formed between said device formation region and said active region.

5. The semiconductor device as set forth in claim 1, further comprising a power supply, wherein said electrode is connected to the power supply or to a drain terminal of the field effect transistor.

6. A method of manufacturing a semiconductor device comprising a field effect transistor utilizing a heterojunction, said field effect transistor formed in a device formation region sectioned by a device separation region on a semiconductor substrate, said method comprising the steps of:

forming said device separation region by forming a layer device separated by implantation of an ion into said semiconductor substrate; and

forming an electrode to which a positive voltage can be applied, on a surface of at least a part of said device separation region in the periphery of said field effect transistor.

7. The method of manufacturing a semiconductor device as set forth in claim 6, including forming the layer device in the part of said device separation region where said electrode is formed.

8. The method of manufacturing a semiconductor device as set forth in claim 6, including forming an active region in the part of said device separation region where said electrode is formed.

9. The method of manufacturing a semiconductor device as set forth in claim 8, including forming the layer device between said device formation region and said active region.

10. The method of manufacturing a semiconductor device as set forth in claim 6, including connecting said electrode to a power supply in said semiconductor device or to a drain terminal of said field effect transistor.