Semiconductor integrated circuit, layout method, layout apparatus and layout program

• US 20060157739A1
• Filed: 01/10/2006
• Published: 07/20/2006
• Est. Priority Date: 01/18/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Tamiya, Masayuki
• Granted Patent: US 7,694,260 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An intermediate wiring layer, lowermost vias and uppermost vias of a semiconductor integrated circuit are disposed within a zone of wiring tracks, which are superposed by wiring traces of an uppermost wiring layer and wiring traces of a lowermost wiring layer, as seen from the direction normal to the plane. The lowermost vias are disposed so as to fit in a 4-row, 1-column rectangle, and the uppermost vias are disposed so as to fit in a 2-row, 2-column rectangle. The center of a via unit, which comprises the uppermost vias, as seen from the direction normal to the plane is disposed at the intersecting portion of the lowermost wiring layer and uppermost wiring layer. The center of a via unit, which comprises the lower vias, as seen from the direction normal to the plane is offset by a prescribed amount from the center of the via unit, which comprises the uppermost vias, as seen from the direction normal to the plane.

Claims

1. A semiconductor integrated circuit comprising:

a first wiring layer having one pair of wiring traces of first and second potentials that differ from each other;

a second wiring layer disposed in a layer different from said first wiring layer and having one pair of wiring traces of the first and second potentials; and

one or a plurality of intermediate wiring layers disposed between said first wiring layer and said second wiring layer;

wherein the pair of wiring traces of said first wiring layer are disposed in parallel with a prescribed spacing between them;

the pair of wiring traces of said second wiring layer are disposed in parallel with a minimum spacing between them that can render wiring tracks effective;

the wiring traces of said first wiring layer are in a direction perpendicular to the wiring traces of said second wiring layer;

same-potential wiring traces of said first wiring layer and of said second wiring layer are electrically connected through said intermediate wiring layer and vias;

as seen from the direction normal to the plane, said intermediate wiring layer is disposed within a zone of wiring tracks superposed by wiring of said first wiring layer and wiring of said second wiring layer;

a number of first vias that connect the wiring of said intermediate wiring layer and the wiring of said first wiring layer is m where m is an integer equal to or greater than 1;

a number of second vias that connect the wiring of said intermediate wiring layer and the wiring of said second wiring layer is m where m is an integer equal to or greater than 1;

the first vias are disposed within a zone of wiring tracks superposed by wiring traces of said second wiring layer and of said first wiring layer as seen from the direction normal to the plane and fit within a rectangular shape of j columns and h rows where j, h are integers equal to or greater than 1 and j×

h≧

m holds;

the second vias are disposed within a zone of wiring tracks superposed by wiring traces of said second wiring layer and of said first wiring layer as seen from the direction normal to the plane and fit within a rectangular shape of n columns and k rows where n, k are integers equal to or greater than 1 and n×

k≧

m holds;

the center of a via unit, which comprises the second vias, as seen from the direction normal to the plane is disposed at an intersecting portion of said first wiring layer and said second wiring layer; and

the center of a via unit for the first potential, as seen from the direction normal to the plane, of via units comprising the first vias is offset by a prescribed amount from the center of the via unit for the first potential, as seen from the direction normal to the plane, toward the side of the wiring of the second potential in said second wiring layer.

2. The semiconductor integrated circuit according to claim 1, wherein the first vias connected to the wiring on the side of the first potential and the first vias connected to the wiring on the side of the second potential are disposed on the same axes the direction of which is the same as that of the wiring of said second wiring layer.

3. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer is disposed so as to overlap one or both of the pair of wiring traces of said second wiring layer.

4. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer comprises two or more layers;

said intermediate wiring layers are connected by third vias;

the third vias are disposed at positions at which they overlap the first vias as seen from the direction normal to the plane; and

wiring length of whichever of said intermediate wiring layers that immediately underlies said second wiring layer is equal to or greater than wiring length of whichever of said intermediate wiring layers are other than the intermediate wiring layer that immediately underlies said second wiring layer.

5. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer comprises two or more layers;

said intermediate wiring layers are connected by third vias;

the third vias are disposed at positions at which they overlap the first vias as seen from the direction normal to the plane; and

wiring width of whichever of said intermediate wiring layers that immediately underlies said second wiring layer is equal to or greater than wiring width of whichever of said intermediate wiring layers are other than the intermediate wiring layer that immediately underlies said second wiring layer.

6. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer that immediately underlies said second wiring layer is formed in a rectangular shape, a T-shaped configuration or an L-shaped configuration as seen from the direction normal to the plane.

7. A layout method comprising the steps of:

generating a first wiring layer in which one pair of wiring traces of first and second potentials that differ from each other are disposed in parallel with a prescribed spacing between them, and a second wiring layer disposed in a layer different from the first wiring layer and in which one pair of wiring traces of the first and second potentials are disposed in parallel with a minimum spacing between them that can render wiring tracks effective and are in a direction perpendicular to the wiring traces of the first wiring layer;

extracting intersecting portions between the second wiring layer and the first wiring layer as well as wiring widths; and

on the basis of information relating to the extracted intersecting portions and wiring widths, generating one or a plurality of intermediate wiring layers disposed between the first wiring layer and the second wiring layer and, as seen from the direction normal to the plane, disposed in a zone of wiring tracks superposed by wiring of the first wiring layer and wiring of the second wiring layer, m-number (where m is an integer equal to or greater than

     1) of first vias connecting the wiring of the intermediate wiring layer and the wiring of the first wiring layer, and m-number (where m is an integer equal to or greater than

     1) of second vias connecting the wiring of the intermediate wiring layer and the wiring of the second wiring layer;

wherein at the step of generating the second vias, the second vias are generated so as to be disposed within a zone of wiring tracks superposed by wiring traces of the second wiring layer and of the first wiring layer as seen from the direction normal to the plane and so as to fit within a rectangular shape of n columns and k rows (where n, k are integers equal to or greater than 1 and n×

k≧

m holds) and in such a manner that the center of a via unit, which comprises the second vias, as seen from the direction normal to the plane is disposed at an intersecting portion of the first wiring layer and second wiring layer as seen from the direction normal to the plane; and

at the step of generating the first vias, the first vias are generated so as to be disposed within a zone of wiring tracks superposed by wiring traces of the second wiring layer and of the first wiring layer as seen from the direction normal to the plane and so as to fit within a rectangular shape of j columns and h rows (where j, h are integers equal to or greater than 1 and j×

h≧

m holds) and in such a manner that the center of a via unit for the first potential, as seen from the direction normal to the plane, of via units comprising the first vias is offset by a prescribed amount from the center of the via unit for the first potential, as seen from the direction normal to the plane, toward the side of the wiring of the second potential in the second wiring layer.

8. A layout apparatus comprising:

a first generating unit for generating a first wiring layer in which one pair of wiring traces of first and second potentials that differ from each other are disposed in parallel with a prescribed spacing between them, and a second wiring layer disposed in a layer different from the first wiring layer and in which one pair of wiring traces of the first and second potentials are disposed in parallel with a minimum spacing between them that can render wiring tracks effective and are in a direction perpendicular to the wiring traces of the first wiring layer;

an extracting unit for extracting intersecting portions between the second wiring layer and the first wiring layer as well as wiring widths; and

a second generating unit for producing, on the basis of information relating to the extracted intersecting portions and wiring widths, one or a plurality of intermediate wiring layers disposed between the first wiring layer and the second wiring layer and, as seen from the direction normal to the plane, disposed in a zone of wiring tracks superposed by wiring of the first wiring layer and wiring of the second wiring layer, m-number (where m is an integer equal to or greater than

     1) of first vias connecting the wiring of the intermediate wiring layer and the wiring of the first wiring layer, and m-number (where m is an integer equal to or greater than

     1) of second vias connecting the wiring of the intermediate wiring layer and the wiring of the second wiring layer;

wherein said second generating unit generates the second vias so as to dispose said second vias within a zone of wiring tracks superposed by wiring traces of the second wiring layer and of the first wiring layer as seen from the direction normal to the plane and so as to fit said second vias within a rectangular shape of n columns and k rows (where n, k are integers equal to or greater than 1 and n×

k≧

m holds) and in such a manner that the center of a via unit, which comprises the second vias, as seen from the direction normal to the plane is disposed at an intersecting portion of the first wiring layer and second wiring layer as seen from the direction normal to the plane; and

said second generating unit generates the first vias so as to dispose said first vias within a zone of wiring tracks superposed by wiring traces of the second wiring layer and of the first wiring layer as seen from the direction normal to the plane and so as to fit said first vias within a rectangular shape of j columns and h rows (where j, h are integers equal to or greater than 1 and j×

h≧

m holds) and in such a manner that the center of a via unit for the first potential, as seen from the direction normal to the plane, of via units comprising the first vias is offset by a prescribed amount from the center of the via unit for the first potential, as seen from the direction normal to the plane, toward the side of the wiring of the second potential in the second wiring layer.