Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof

• US 20060157750A1
• Filed: 06/30/2005
• Published: 07/20/2006
• Est. Priority Date: 01/20/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jong-pyo, Yang, Jong-ho, Ko, Young-gun
• Application Number:
  US11/171,810
• Publication Number:
  US 20060157750A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Provided is a semiconductor device having an etch-resistant L-shaped spacer and a fabrication method thereof. The semiconductor device comprises a semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, an L-shaped lower spacer conformally formed on sidewalls of the gate electrode and a portion of the substrate, an etch-resistant L-shaped spacer conformally formed on the L-shaped lower spacer, low-concentration source/drain regions aligned to sides of sidewall portions of the L-shaped lower spacer and formed within the substrate, and high-concentration source/drain regions aligned to sides of a bottom portions of the etch-resistant L-shaped spacer and formed within the substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate insulating layer formed on the semiconductor substrate;

a gate electrode formed on the gate insulating layer;

an L-shaped lower spacer conformally formed on sidewalls of the gate electrode and a portion of the substrate;

an etch-resistant L-shaped spacer conformally formed on the L-shaped lower spacer;

low-concentration source/drain regions aligned to sides of the sidewall portions of the L-shaped lower spacer and formed within the substrate; and

high-concentration source/drain regions aligned to sides of bottom portions of the etch-resistant L-shaped spacer and formed within the substrate.

2. The semiconductor device of claim 1, further comprising a contact etch stopper layer exposing at least a portion of the high-concentration source/drain regions and covering at least a portion of the etch-resistant L-shaped spacer, or exposing at least a portion of the high-concentration source/drain regions and a top surface of the gate electrode and covering at least a portion of the etch-resistant L-shaped spacer.

3. The semiconductor device of claim 2, wherein the contact etch stopper layer is formed of nitride.

4. The semiconductor device of claim 3, wherein a dry etching selectivity of the etch-resistant L-shaped spacer to the contact etch stopper layer is greater than or equal to about 1:

10.

5. The semiconductor device of claim 4, wherein a wet etching selectivity of the etch-resistant L-shaped spacer to the contact etch stopper layer is greater than or equal to about 1:

10.

6. The semiconductor device of claim 1, wherein the etch-resistant L-shaped spacer is made of material having a high dielectric constant (high-k).

7. The semiconductor device of claim 6, wherein the high-k material is a hafnium-based or a zirconium-based compound.

8. The semiconductor device of claim 1, wherein the etch-resistant L-shaped spacer has a thickness in the range of from about 30 to about 150 Å

.

9. A method of fabricating a semiconductor device comprising:

providing a semiconductor substrate having a gate insulating layer and a gate electrode sequentially stacked thereon; and

forming a transistor having an L-shaped lower spacer conformally formed on sidewalls of the gate electrode and a portion of the substrate, an etch-resistant L-shaped spacer conformally formed on the L-shaped lower spacer, low concentration source/drain regions aligned to sides of sidewall portions of the L-shaped lower spacer and formed within the substrate, and high-concentration source/drain regions aligned to sides of bottom portions of the etch-resistant L-shaped spacer and formed within the substrate.

10. The method of claim 9, wherein the forming of the transistor comprises:

forming a first insulating layer to be used as a spacer, the first insulating layer conform to the gate electrode;

forming low-concentration source/drain regions aligned to sides of sidewall portions of the L-shaped lower spacer by implanting impurities in the semiconductor substrate;

forming second and third insulating layers on the first insulating layer to be used as spacers, the second insulating layers being made of an etch resistant material;

forming an upper spacer contacting sidewalls of the second insulating layer by etching the third insulating layer;

forming an etch-resistant L-shaped spacer and an L-shaped lower spacer by sequentially etching the second insulating layer and the first insulating layer using the upper spacer as an etch mask; and

forming high-concentration source/drain regions aligned to sides of bottom portions of the etch-resistant L-shaped spacer.

11. The method of claim 10, further comprising:

performing pre-treatment to remove the upper spacer so that the etch-resistant L-shaped spacer and the L-shaped lower spacer are left on the sidewalls of the gate electrode;

forming a contact etch stopper layer and an interlayer dielectric (ILD) film over the entire surface of the substrate; and

forming a contact hole exposing at least a portion of the high-concentration source/drain regions or a contact hole exposing at least a portion of the high-concentration source/drain regions and a top surface of the gate electrode by dry etching the ILD film and the contact etch stopper layer.

12. The method of claim 11, comprising performing the pre-treatment for at least one cleaning cycle.

13. The method of claim 12, wherein the cleaning cycle is carried out using a hydrofluoric (HF) solution diluted in deionized water, an aqueous fluoride-based solution, or a mixed solution of ammonium hydroxide HF and deionized water.

14. The method of claim 11, wherein a dry etching selectivity of the etch-resistant L-shaped spacer to the contact etch stopper layer is greater than or equal to about 1:

10.

15. The method of claim 11, wherein the contact etch stopper layer is formed of nitride.

16. The method of claim 11, wherein in the forming of the contact hole, a wet etching selectivity of the etch-resistant L-shaped spacer to the contact etch stopper layer is greater than or equal to about 1:

10.

17. The method of claim 9, wherein the etch-resistant L-shaped spacer is made of a high-k material.

18. The method of claim 17, wherein the high-k material layer is a hafnium-based or a zirconium-based compound.

19. The method of claim 17, wherein the high-k material layer is formed by chemical vapor deposition or atomic layer deposition.

20. The method of claim 17, wherein the high-k material layer is formed to a thickness in the range of about 30 to about 150 Å

.