Semiconductor device including high-K insulating layer and method of manufacturing the same

• US 20060157754A1
• Filed: 01/18/2006
• Published: 07/20/2006
• Est. Priority Date: 01/18/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sung-Ho, Choi, Sung-Kyu, Choi, Sang-Moo, Han, Jeong-Hee, Jeon, Sang-Hun, Hwang, Hyun-Sang, Kim, Chung-Woo
• Granted Patent: US 7,456,468 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02156 the material containing at least one rare earth element, e.g. silicate of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Claims

1. A semiconductor memory device comprising:

a first dopant area and a second dopant area, the first dopant area and the second dopant areas disposed in a semiconductor substrate;

an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including at least one of an Hf silicate, a Zr silicate, a Y silicate, and a Ln silicate; and

a gate electrode layer disposed on the insulating layer.

2. The semiconductor memory device of claim 1, the insulating layer comprising a material, the material having a chemical formula ((Hf, Zr, Y or Ln)O₂)_x(SiO₂)_1-x, where (0.03≦

x≦

0.26), the material having a dielectric constant that is greater than 3.9 and less than or equal to 10 (3.9<

dielectric constant≦

10).

3. The semiconductor memory device of claim 1, the insulating layer comprising:

a tunneling oxide layer disposed in contact with the first dopant area and the second dopant area;

a data storing layer disposed on the tunneling oxide layer; and

a blocking oxide layer disposed on the data storing layer, one of the tunneling oxide layer and the blocking oxide layer consisting of a dielectric layer having a chemical formula ((Hf, Zr, Y or Zr)O₂)_x(SiO₂)_1-x, where (0.03≦

x≦

0.26).

4. The semiconductor memory device of claim 1, the insulating layer comprising one of Al and N.

5. The semiconductor device of claim 1, the insulating layer comprising the Hf silicate.

6. The semiconductor device of claim 1, the insulating layer comprising the Zr silicate.

7. The semiconductor device of claim 1, the insulating layer comprising the Y silicate.

8. The semiconductor device of claim 1, the insulating layer comprising the Ln silicate.

9. A method of manufacturing a semiconductor memory device, the method comprising:

forming an insulating layer on a semiconductor substrate, the insulating layer including at least one selected from the group consisting of Hf. Zr, Y, and Ln;

forming a gate electrode layer on the insulating layer;

removing a portion of the insulating layer and a portion of the gate electrode layer to define a gate and to expose upper surfaces of the semiconductor substrate on both sides of the gate;

doping the upper surfaces of the semiconductor substrate with a dopant to form a first dopant area and a second dopant area; and

annealing the upper surfaces of the semiconductor substrate to activate the first dopant area and the second dopant area.

10. The method of claim 9, wherein forming the insulating layer comprises:

depositing a tunneling oxide layer on the semiconductor substrate;

depositing a charge-trap layer on the tunneling oxide layer; and

depositing a blocking oxide layer on the charge-trap layer, one of the tunneling oxide layer and the blocking oxide layer consisting of a dielectric layer having a chemical formula ((Hf, Zr, Y or Zr)O₂)_x(SiO₂)_1-x, where (0.03≦

x≦

0.26).

11. The method of claim 9, wherein forming the insulating layer comprises:

depositing a tunneling oxide layer on the semiconductor substrate;

depositing a charge-trap layer on the tunneling oxide layer; and

depositing a blocking oxide layer on the charge-trap layer, one of the tunneling oxide layer and the blocking oxide layer consisting of a dielectric layer having a chemical formula ((Hf, Zr, Y or Zr)O₂)_x(Al₂O₃)_1-x, where (0.03≦

x≦

0.26).

12. The method of claim 9, wherein the insulating layer has a dielectric constant that is greater than 3.9 and less than or equal to 10 (3.9<

dielectric constant<

10).

13. The method of claim 9, wherein the insulating layer comprises one of Al and N.

14. A semiconductor memory device comprising:

a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate;

an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer comprising a material selected from the group consisting of Hf, Zr, Y, and Ln; and

a gate electrode layer disposed on the insulating layer.

15. The semiconductor memory device of claim 14, the insulating layer comprising:

a tunneling oxide layer disposed in contact with the first dopant area and the second dopant area;

a data storing layer disposed on the tunneling oxide layer; and

a blocking oxide layer disposed on the data storing layer, one of the tunneling oxide layer and the blocking oxide layer consisting of a dielectric layer having a chemical formula ((Hf, Zr, Y or Zr)O₂)_x(SiO₂)_1-x, where (0.03≦

x≦

0.26).

16. The semiconductor memory device of claim 14, the insulating layer comprising:

a tunneling oxide layer disposed in contact with the first dopant area and the second dopant area;

a data storing layer disposed on the tunneling oxide layer; and

a blocking oxide layer disposed on the data storing layer, one of the tunneling oxide layer and the blocking oxide layer consisting of a dielectric layer having a chemical formula ((Hf, Zr, Y or Zr)O₂)_x(Al₂O₃)_1-x, where (0.03≦

x≦

0.26).

17. The semiconductor device of claim 14, the insulating layer comprising Hf.

18. The semiconductor device of claim 14, the insulating layer comprising Zr.

19. The semiconductor device of claim 14, the insulating layer comprising Y.

20. The semiconductor device of claim 14, the insulating layer comprising Ln.