Semiconductor device and manufacturing method of the same
First Claim
1. A semiconductor device having a field-effect transistor with a trench gate structure on a semiconductor substrate, the semiconductor substrate having a first main surface and a second main surface on the reverse side thereof, the field-effect transistor with a trench gate structure comprising:
- a source region of first conductivity type, provided on the first main surface of the semiconductor substrate;
a drain region of the first conductivity type, provided on the second main surface of the semiconductor substrate;
a channel forming region provided between the source region and the drain region of the semiconductor substrate;
a first trench that is extended in a direction orthogonal to the first main surface of the semiconductor substrate so that the first trench is extended from the first main surface of the semiconductor substrate, penetrates the source region and the channel forming region, and is terminated at the drain region;
a gate insulating layer formed in the first trench;
a gate electrode provided in the first trench via the gate insulating layer;
an interlayer insulating layer provided over the gate electrode; and
a source electrode that is provided over the first main surface of the semiconductor substrate with the interlayer insulating layer in-between, and is brought into contact with and electrically connected with the upper face of the source region, exposed from the interlayer insulating layer, wherein the upper face of the gate electrode is formed at a level lower than the first main surface of the semiconductor substrate, and wherein, letting the distance between an end of the interlayer insulating layer over the upper face of the source region and the end of the upper face of the source region farther from the first gate electrode be “
a” and
letting the length of the overlap between the interlayer insulating layer and the upper face of the source region be “
b”
, b≦
a.
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Accused Products
Abstract
The on-resistance of a semiconductor device having a power transistor with a trench gate structure is reduced. A power MIS-FET with a trench gate structure is so formed that the relation expressed as 0≦b≦a holds, where a is the distance between an end of an interlayer insulating layer over the upper face of a semiconductor region for source and the end (position on the periphery of a trench) of the upper face of the semiconductor region for source farther from the gate electrode; and b is the length of the overlap between the interlayer insulating layer and the upper face of the semiconductor region for source. (b is the distance between the position of the end of the interlayer insulating layer over the upper face of the semiconductor region for source and position on the periphery of a trench). As a result, the area of contact between source pads and the semiconductor regions for source is increased, and further the distance between the source pads and a channel forming region can be shortened. Therefore, the on-resistance of the power MIS-FET with a trench gate structure can be reduced.
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Citations
23 Claims
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1. A semiconductor device having a field-effect transistor with a trench gate structure on a semiconductor substrate, the semiconductor substrate having a first main surface and a second main surface on the reverse side thereof,
the field-effect transistor with a trench gate structure comprising: -
a source region of first conductivity type, provided on the first main surface of the semiconductor substrate;
a drain region of the first conductivity type, provided on the second main surface of the semiconductor substrate;
a channel forming region provided between the source region and the drain region of the semiconductor substrate;
a first trench that is extended in a direction orthogonal to the first main surface of the semiconductor substrate so that the first trench is extended from the first main surface of the semiconductor substrate, penetrates the source region and the channel forming region, and is terminated at the drain region;
a gate insulating layer formed in the first trench;
a gate electrode provided in the first trench via the gate insulating layer;
an interlayer insulating layer provided over the gate electrode; and
a source electrode that is provided over the first main surface of the semiconductor substrate with the interlayer insulating layer in-between, and is brought into contact with and electrically connected with the upper face of the source region, exposed from the interlayer insulating layer, wherein the upper face of the gate electrode is formed at a level lower than the first main surface of the semiconductor substrate, and wherein, letting the distance between an end of the interlayer insulating layer over the upper face of the source region and the end of the upper face of the source region farther from the first gate electrode be “
a” and
letting the length of the overlap between the interlayer insulating layer and the upper face of the source region be “
b”
, b≦
a. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device having a field-effect transistor with a trench gate structure on a semiconductor substrate, the semiconductor substrate having a first main surface and a second main surface on the reverse side thereof,
the field-effect transistor with a trench gate structure comprising: -
a source region of first conductivity type, provided on the first main surface of the semiconductor substrate;
a drain region of the first conductivity type, provided on the second main surface of the semiconductor substrate;
a channel forming region provided between the source region and the drain region of the semiconductor substrate;
a first trench extended in a direction orthogonal to the first main surface of the semiconductor substrate so that the first trench is extended from the first main surface of the semiconductor substrate, penetrates the source region and the channel forming region, and is terminated at the drain region;
a gate insulating layer formed in the first trench;
a gate electrode provided in the first trench via the gate insulating layer;
an interlayer insulating layer that is provided over the gate electrode; and
a source electrode that is provided over the first main surface of the semiconductor substrate with the interlayer insulating layer in-between, and is brought into contact with and electrically connected with the upper face of the source region, exposed from the interlayer insulating layer, and wherein a cutoff trench is provided between an end of a source region on the periphery of a group of a plurality of cells of the field-effect transistor with a trench gate structure and an end of an insulating layer for isolation provided outside the end of the source region on the periphery of the group of a plurality of the cells. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A manufacturing method of a semiconductor device having a field-effect transistor with a trench gate structure in an element formation region of a semiconductor substrate having a first main surface and a second main surface on the reverse side thereof, comprising the steps of:
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(a) preparing the semiconductor substrate;
(b) forming a first trench in a first main surface of the semiconductor substrate which first trench is extended in a direction orthogonal to the first main surface;
(c) forming a first insulating layer over the first main surface of the semiconductor substrate and the inner surface of the first trench;
(d) depositing a first conductor layer over the first main surface of the semiconductor substrate and in the first trench;
(e) removing part of the first conductor layer so that part of the first conductor layer is left in the first trench in an element formation region in the first main surface of the semiconductor substrate, and thereby forming an electrode comprised of the first conductor layer in the first trench;
(f) removing part of the first insulating layer in the element formation region, and thereby forming an insulating layer for isolation comprised of the first insulating layer in an isolation region of the semiconductor substrate;
(g) forming a gate insulating film over the first main surface of the semiconductor substrate and the inner surface of the first trench;
(h) depositing a second conductor layer over the first main surface of the semiconductor substrate and in the first trench;
(i) removing part of the second conductor layer so that part of the second conductor layer is left in the first trench in the element formation region in the first main surface of the semiconductor substrate, and thereby forming a gate electrode comprised of the second conductor layer in the first trench;
(j) implanting a desired impurity on the first main surface of the semiconductor substrate using the insulating layer for isolation as a mask, and thereby forming a channel forming region of the field-effect transistor with a trench gate structure; and
(k) implanting a desired impurity on the first main surface of the semiconductor substrate using the insulating layer for isolation as a mask, and thereby forming a source region of the field-effect transistor with a trench gate structure, wherein in the step of (b), the first trench for element in which the gate electrode of the field-effect transistor with the trench gate structure is to be buried is formed, and further a cutoff trench is formed between an end of the source region in the element formation region and an end of the insulating layer for isolation. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification