Trench fet with self aligned source and contact

• US 20060157782A1
• Filed: 03/15/2006
• Published: 07/20/2006
• Est. Priority Date: 09/05/2001
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Amali, Adam I., Thapar, Naresh
• Granted Patent: US 7,301,200 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

Claims

1. A power semiconductor device comprising:

a semiconductor die, said semiconductor die including a drift region of a first conductivity type;

a channel region of a second conductivity type over said drift region;

a plurality of trenches extending to a depth below said channel region;

gate insulation formed on sidewalls of each trench;

a gate electrode disposed inside each trench;

a silicide body formed over each gate electrode;

an oxide plug comprised of TEOS formed over each silicide body;

conductive regions of said first conductivity each formed adjacent a respective trench; and

a first contact formed over said die and in electrical contact with each one of said conductive regions of said first conductivity, said first contact extending over said oxide plug, wherein no other insulation is disposed between said oxide plug and said silicide body, and wherein said oxide plug does not extend over said conductive regions.

2. A device according to claim 1, further comprising a thickened oxide layer at the bottom of each trench.

3. A device according to claim 1, further comprising a termination region, wherein no conductive region of said first conductivity is present in said termination region.

4. A device according to claim 1, further comprising a substrate, said drift region being disposed over said substrate, and a second contact in electrical contact with said substrate.

5. A device according to claim 4, wherein said conductive regions are source regions, said first contact is a source contact and said second contact is a drain contact.

6. A device according to claim 1, wherein said silicide body is contained within said trench.

7. A device according to claim 1, wherein said conductive region and said channel region electrically connect to said first contact on a common plane.