SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and methods for making same
First Claim
1. An SRAM array comprising a plurality of SRAM cells, each of said SRAM cells comprising:
- a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and
where at least two adjacent NFETs of the SRAM cell share a leakage path between body regions, and where at least two adjacent NFETs have a source/drain diffusion region and a leakage path diffusion region under the source drain diffusion region positioned between their respective body regions, wherein the source/drain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the source/drain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the source/drain diffusion but at relatively lower concentrations than the source/drain diffusion, thereby presenting a lower barrier to junction leakage than the source/drain regions.
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Abstract
The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions. Another aspect of this invention concerns a microprocessor fabricated on an hybrid orientation substrate where the logic portion of the circuit has NFETs fabricated in (100) crystal orientation SOI silicon regions with floating body regions and PFETs fabricated in (110) crystal orientation bulk silicon regions; and where the SRAM memory portion has NFETs fabricated in (100) crystal orientation SOI silicon regions with body regions linked by leakage path diffusion regions beneath shallow source/drain diffusions and PFETs fabricated in (110) crystal orientation silicon regions.
38 Citations
60 Claims
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1. An SRAM array comprising a plurality of SRAM cells, each of said SRAM cells comprising:
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a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and
where at least two adjacent NFETs of the SRAM cell share a leakage path between body regions, and where at least two adjacent NFETs have a source/drain diffusion region and a leakage path diffusion region under the source drain diffusion region positioned between their respective body regions, wherein the source/drain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the source/drain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the source/drain diffusion but at relatively lower concentrations than the source/drain diffusion, thereby presenting a lower barrier to junction leakage than the source/drain regions. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A pair of adjacent SRAM cells in an SRAM array, the pair comprising a first SRAM cell and a second SRAM cell, each of the adjacent SRAM cells comprising:
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a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and
where at least one of the NFETs from the first SRAM cell and at least one of the NFETs from the second SRAM cell share a leakage path between body regions, the respective NFETs sharing a leakage path being adjacent to one another and where the at least two adjacent NFETs have a source/drain diffusion region and a leakage path diffusion region under the source/drain diffusion region positioned between their respective body regions, wherein the source/drain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the source/drain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the source/drain diffusion but at relatively lower concentrations than the source/drain diffusion, thereby presenting a lower barrier to junction leakage than the source/drain regions. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A pair of adjacent SRAM cells in an SRAM array, the pair comprising a first SRAM cell and a second SRAM cell, each of the adjacent SRAM cells comprising:
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a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled inverters; and
where at least one of the PFETs from the first SRAM cell and at least one of the PFETs from the second SRAM cell share a leakage path between body regions, the respective PFETs sharing a leakage path being adjacent to one another and where the at least two adjacent PFETs have a source/drain diffusion region and a leakage path diffusion region under the source/drain diffusion region positioned between their respective body regions, wherein the source/drain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the source/drain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the source/drain diffusion but at relatively lower concentrations than the source/drain diffusion, thereby presenting a lower barrier to junction leakage than the source/drain regions. - View Dependent Claims (17, 18)
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19. A pair of adjacent SRAM cells in an SRAM array, the pair comprising a first SRAM cell and a second SRAM cell, where each of the SRAM cells have two longitudinal and two lateral sides, the adjacent SRAM cells sharing a longitudinal side, each of the adjacent SRAM cells comprising:
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a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, wherein the cross-coupled CMOS inverters each comprise an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters, and wherein one each of the pass gate NFETs and inverter NFETs are positioned along each of the lateral sides of the SRAM cell, whereby the pass gate NFET and inverter NFET positioned on the same lateral side of the SRAM cell comprise a pair and have body regions linked with leakage path diffusion regions formed beneath adjacent shallow source/drain diffusions wherein the shallow source/drain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the source/drain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the source/drain diffusion but at relatively lower concentrations than the source/drain diffusion, thereby presenting a lower barrier to junction leakage than the source/drain regions. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. An SRAM array comprising a plurality of SRAM cells organized in rows and columns,
wherein each of the SRAM cells have two longitudinal sides and two lateral sides, the SRAM cells further comprising: -
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters; and
where at least two adjacent NFETs of the SRAM cell share a leakage path between body regions, and where the at least two adjacent NFETs have a source/drain diffusion region and a leakage path diffusion region under the source/drain diffusion region positioned between their respective body regions, wherein the source/drain diffusion region extends fractionally into the surface silicon layer and the leakage path diffusion region extends from a bottom of the source/drain diffusion down to the SOI buried-oxide layer, and where the leakage path diffusion region is counter-doped with the same dopant type as the source/drain diffusion but at relatively lower concentrations than the source/drain diffusion, thereby presenting a lower barrier to junction leakage than the source/drain regions, and where each of the SRAM cells arrayed in a particular row of the SRAM array share longitudinal sides with two other SRAM cells positioned in the same row, except for at least two of the SRAM cells one longitudinal side of each coincides with a termination point of the row, and where the at least two adjacent NFETs of each SRAM cell arrayed in the particular row of the SRAM array having body regions linked by the leakage path diffusion region have their body regions further linked to the body regions of NFETs contained in adjacent SRAM cells sharing longitudinal sides with the SRAM cell with leakage path diffusion regions positioned beneath adjacent shallow source/drain diffusion regions, except for the at least two of the SRAM cells having one longitudinal side coinciding with the termination point of the row which have at least one pair of NFETs having a body region linked to the body regions of NFETs positioned in one SRAM cell on a longitudinal side opposite from the termination point of the row with leakage path diffusion regions positioned beneath adjacent shallow source/drain diffusion regions; and
whereby a continuous chain of NFETS having body regions linked with leakage path diffusion regions positioned beneath adjacent shallow source/drain diffusion regions exists across the particular row of the SRAM array. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A microprocessor fabricated on a CMOS hybrid orientation substrate, wherein the microprocessor comprises a logic portion and a cache memory portion, wherein the cache memory portion further comprises at least one CMOS SRAM array and where:
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the logic portion comprises, in part, PFETs fabricated in (110) crystal orientation bulk silicon regions and NFETs fabricated in (100) crystal orientation SOI silicon regions, wherein the NFETs in the logic portion have floating body regions; and
the CMOS SRAM array comprises a plurality of CMOS SRAM cells comprising, in part, PFETs fabricated in (110) crystal orientation silicon regions and NFETs fabricated in (100) crystal orientation SOI silicon regions, wherein at least a portion of the NFETs in the CMOS SRAM cells have body regions linked to body regions of adjacent NFETs with leakage path diffusion regions formed beneath adjacent shallow source/drain diffusions wherein the source/drain diffusion regions extend fractionally into a surface silicon layer and the leakage path diffusion regions extend from bottoms of the source/drain diffusions down to an SOI buried-oxide layer, and where the leakage path diffusion regions are counter-doped with the same dopant type as the source/drain diffusions but at relatively lower concentrations than the source/drain diffusions, thereby presenting a lower barrier to junction leakage than the source/drain regions.
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36. A method of forming an SRAM array comprising a plurality of SRAM cells, each of the SRAM cells comprising a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET and the SRAM cell further comprises a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters, the method comprising:
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forming a buried oxide layer in a silicon wafer, the buried oxide layer positioned between a surface silicon layer and a silicon substrate;
forming a plurality of PFET and NFET gates above body regions in the surface silicon layer;
forming a leakage path diffusion region between at least a pair of adjacent NFET body regions wherein the leakage path diffusion region is counter-doped with a same dopant type as a shallow source/drain diffusion to be formed in another step but at relatively lower concentration than the shallow source/drain diffusions, thereby presenting a lower barrier to junction leakage than the source/drain regions, the leakage path diffusion region extending to the buried oxide layer; and
forming the shallow source/drain diffusions above the leakage path diffusion regions, the shallow source/drain diffusions extending fractionally into the surface silicon layer - View Dependent Claims (37, 38, 39, 40, 41)
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42. An SRAM memory comprising:
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peripheral logic fabricated in a high-performance silicon substrate;
an SRAM array comprised of a plurality of SRAM cells, wherein the SRAM cells are arrayed in rows and columns and further comprise;
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, wherein the cross-coupled CMOS inverters each comprise an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters, where body regions of NFETs arrayed along a column of SRAM cells coinciding with a bit line are linked by leakage path diffusion regions beneath adjacent shallow source drain diffusion regions, thereby forming a chain of linked body regions. - View Dependent Claims (43, 44, 45, 46, 47, 48)
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49. An SRAM memory comprising:
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peripheral logic comprised of CMOS NFETs and PFETs, where the NFETs are fabricated in bulk silicon regions and the PFETs are fabricated in SOI silicon regions, where body regions of the PFETs are floating; and
an SRAM array comprised of a plurality of SRAM cells, wherein the SRAM cells are arrayed in rows and columns and further comprise;
a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, wherein the cross-coupled CMOS inverters each comprise an NFET and a PFET;
a pair of NFET pass gates selectively coupling a pair of bit lines to said cross-coupled CMOS inverters, where body regions of NFETs along a column of SRAM cells coinciding with a bit line are linked by leakage path diffusion regions beneath adjacent shallow source drain diffusion regions, thereby forming a chain of linked body regions. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57)
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58. A method of forming an SRAM memory comprised of an SRAM array portion and a peripheral logic portion, where the SRAM array portion is comprised of a plurality of SRAM cells, and where each of the SRAM cells further comprises a pair of cross-coupled CMOS inverters in a surface silicon layer disposed on an SOI buried-oxide layer, where each cross-coupled inverter comprises an NFET and a PFET and the SRAM cell further comprises a pair of NFET pass gates coupling a pair of bit lines to the cross-coupled CMOS inverters, the method comprising:
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forming a high-performance silicon substrate portion in a silicon wafer;
forming circuits comprising the peripheral logic portion of the SRAM memory in the high-performance silicon substrate portion of the silicon wafer;
forming the SRAM array portion of the SRAM memory by;
forming a buried oxide layer in the silicon wafer, the buried oxide layer positioned between a surface silicon layer and a silicon substrate;
forming a plurality of PFET and NFET gates above body regions in the surface silicon layer;
forming a leakage path diffusion region between at least a pair of adjacent NFET body regions wherein the leakage path diffusion regions are counter-doped with a same dopant type as a shallow as a shallow source/drain diffusion to be formed in another step but at a relatively lower concentration than the shallow source/drain diffusions, thereby presenting a lower barrier to junction leakage than the source/drain regions, the leakage path diffusion region extending to the buried oxide layer; and
forming the shallow source/drain diffusions above the leakage path diffusion regions, the shallow source/drain diffusions extending fractionally into the surface silicon layer. - View Dependent Claims (59, 60)
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Specification