Non-planar MOS structure with a strained channel region

• US 20060157794A1
• Filed: 03/09/2006
• Published: 07/20/2006
• Est. Priority Date: 01/18/2005
• Status: Active Grant

• Current Assignee: Been-Yih Jin, Brian S. Doyle, Robert Chau, Suman Datta
• Original Assignee: Been-Yih Jin, Brian S. Doyle, Robert Chau, Suman Datta
• Inventors: Jin, Been-Yih, Doyle, Brian S., Datta, Suman, Chau, Robert
• Granted Patent: US 7,531,393 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

Claims

1-14. -14. (canceled)

15. A method comprising:

forming silicon germanium on a silicon on insulator substrate;

annealing the silicon germanium to relax the silicon germanium;

forming a fin in the relaxed silicon germanium, the fin including a top surface and two sidewall surfaces; and

forming strained silicon on the top surface and two sidewall surfaces of the fin.

16. The method of claim 15, annealing the silicon germanium further comprising diffusing germanium into the silicon of the silicon on insulator substrate.

17. The method of claim 16 further comprising:

forming a gate dielectric on the strained silicon film, the gate dielectric material selected from the group consisting of silicon dioxide, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantanate, and lead zinc niobate.

18. The method of claim 17 further comprising:

forming a gate on the gate dielectric, the gate material selected from the group consisting of polysilicon, metal, and a combination thereof.

19. The method of claim 18 further comprising:

doping the strained silicon to form a source and a drain.

20-22. -22. (canceled)