Semiconductor integrated circuit device and method for testing the same

• US 20060158201A1
• Filed: 11/22/2005
• Published: 07/20/2006
• Est. Priority Date: 01/19/2005
• Status: Abandoned Application

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Kamei, Shunji, Sobue, Satoshi, Yamamoto, Tomohisa
• Application Number:
  US11/283,907
• Publication Number:
  US 20060158201A1
• Time in Patent Office: Days
• US Class Current: 324/678
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Abstract

A semiconductor integrated circuit device includes a semiconductor layer formed on a support substrate so as to be insulated from the support substrate; plural circuit blocks formed in the semiconductor layer so as to be insulated from one another; and at least one pair of power supply terminals provided in connection with each of the circuit blocks to supply power to the respective circuit block. The circuit blocks operate as a whole while connected together in series by successively connecting the power supply terminals of different circuit blocks to one another, and also each of the circuit blocks can operate independently under a state that a voltage is applied between the pair of power supply terminals.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor layer formed on a support substrate so as to be insulated from the support substrate;

plural circuit blocks formed in the semiconductor layer so as to be insulated from one another; and

at least one pair of power supply terminals provided in connection with each of the circuit blocks to supply power to the respective circuit block, wherein the circuit blocks can operate as a whole while connected together in series by successively connecting the power supply terminals of different circuit blocks to one another, and also each of the circuit blocks can operate independently under a state that a voltage is applied between the pair of power supply terminals.

2. The semiconductor integrated circuit device according to claim 1, wherein each circuit block has at least one of a cell voltage equalizing circuit for equalizing the voltages of respective cells of a battery package constructed by connecting plural secondary cells to one another in series and a cell over-charging/over-discharging equalizing circuit for detecting an excessively charging/discharging state of each cell of the battery pack.

3. A method of testing a semiconductor integrated circuit device by applying a voltage to a power supply terminal, the semiconductor integrated circuit device comprising:

a semiconductor layer formed on a support substrate so as to be insulated from the support substrate;

plural circuit blocks formed in the semiconductor layer so as to be insulated from one another; and

at least one pair of power supply terminals provided in connection with each of the circuit blocks to supply power to the circuit block concerned, wherein when the semiconductor integrated circuit device is in use, the power supply terminals of the different circuit blocks are successively connected to one another to make the circuit blocks operate as a whole under a state that the circuit blocks are connected to one another in series, and when the semiconductor integrated circuit device is under a test state, a test voltage is applied between the power supply terminals of the respective circuit blocks.

4. The semiconductor integrated circuit device testing method according to claim 3, wherein under the test state of the semiconductor integrated circuit device, the power supply terminals of the respective circuit blocks are commonly connected to each other to connect the circuit blocks in parallel, and a voltage is applied between the commonly-connected power supply terminals.

5. The semiconductor integrated circuit device testing method according to claim 3, wherein the semiconductor integrated circuit device has at least one of a cell voltage equalizing circuit for equalizing the voltages of respective cells of a battery package constructed by connecting plural secondary cells to one another in series and a cell over-charging/over-discharging equalizing circuit for detecting an excessively charging/discharging state of each cell of the battery pack, and each circuit block is constructed by connecting in series a predetermined number of cell voltage equalizing circuits or cell over-charging/over-discharging detecting circuits each of which is provided in connection with each cell.

6. The semiconductor integrated circuit device test method according to claim 5, wherein the in-series connection number of cell voltage equalizing circuits or the cell over-discharging/over-charging detecting circuits are set to be equal between the respective circuit blocks.

7. The semiconductor integrated circuit device testing method according to claim 3, wherein a burn-in test or a test using an IC tester is executed.

8. The semiconductor integrated circuit device testing method according to claim 4, wherein the semiconductor integrated circuit device has at least one of a cell voltage equalizing circuit for equalizing the voltages of respective cells of a battery package constructed by connecting plural secondary cells to one another in series and a cell over-charging/over-discharging equalizing circuit for detecting an excessively charging/discharging state of each cell of the battery pack, and each circuit block is constructed by connecting in series a predetermined number of cell voltage equalizing circuits or cell over-charging/over-discharging detecting circuits each of which is provided in connection with each cell.