CAPACITANCE DETECTING CIRCUIT AND METHOD, AND FINGERPRINT SENSOR USING THE SAME

• US 20060158202A1
• Filed: 11/10/2004
• Published: 07/20/2006
• Est. Priority Date: 11/25/2003
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Inventors: Saito, Junichi, Umeda, Yuichi
• Granted Patent: US 7,084,645 B1
• Time in Patent Office: Days
• US Class Current: 324/686
• CPC Class Codes: G06F 3/04182 Filtering of noise external to the device and not generated by digitiser components
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing

Abstract

In a capacitance detecting circuit, changes in capacitances at intersections between a plurality of column lines and a row line are detected as voltages. The capacitance detecting circuit includes a code generator for generating code having orthogonality in chronological order. A column-line driver drives the plurality of column lines based on the code by dividing the column lines into a first column line group and a second column line group. A capacitance detector, which is connected to the row line, converts the total of currents generated in capacitances at the intersections with the driven column lines into a voltage signal and outputs the converted voltage signal. A decoding computation unit determines the voltages corresponding to the capacitances at the intersections for each of the column line groups by performing product sum computation between the measured voltages and the code. In a period for detecting the capacitances, the column-line driver drives the first column line group and the second column line group by complementary voltages according to the code or information indicating the inversion of the code.

Claims

1. A capacitance detecting circuit for detecting changes in capacitances at intersections between a plurality of column lines and a row line as voltages, comprising:

code generating means for generating code having orthogonality in chronological order;

column-line driving means for driving the plurality of column lines based on the code by dividing the column lines into a first column line group and a second column line group;

capacitance detecting means connected to the row line, for converting a total of currents generated in capacitances at the intersections with the driven column lines into a voltage signal and outputting the converted voltage signal; and

decoding computation means for determining the voltages corresponding to the capacitances at the intersections for each of the column line groups by performing product sum computation between the measured voltages and the code,

wherein, in a period for detecting the capacitances, the column-line driving means drives one of the first column line group and the second column line group to shift from a first voltage to a second voltage and drives the other one of the first column line group and the second column line group to shift from the second voltage to the first voltage according to the code or information indicating the inversion of the code.

2. The capacitance detecting circuit according to claim 1, wherein the capacitance detecting means detects the capacitances at the intersections of an area capacitance sensor in which a plurality of row lines are disposed in accordance with the plurality of column lines in a matrix.

3. The capacitance detecting circuit according to claim 1, wherein the capacitance detecting means detects the capacitances at the intersections of a line capacitance sensor in which a row line is disposed in accordance with the plurality of column lines.

4. The capacitance detecting circuit according to claim 1, wherein the column-line driving means divides the period for detecting the capacitances into a first capacitance detection period and a second capacitance detection period, and in the first capacitance detection period, the column-line driving means drives the first column line group to rise from the first voltage to the second voltage and the second column line group to fall from the second voltage to the first voltage, and in the second capacitance detection period, the column-line driving means drives the first column line group to fall from the second voltage to the first voltage and the second column line group to rise from the first voltage to the second voltage.

5. The capacitance detecting circuit according to claim 1, wherein the plurality of column lines are divided into a plurality of column line groups, each having a predetermined number of column lines, and

the column-line driving means selectively changes the plurality of column line groups at predetermined intervals in chronological order, and drives the selected column line group by dividing the column lines into the first column line group and the second column line group based on the code without driving the column lines of the unselected column line groups.

6. The capacitance detecting circuit according to claim 1, wherein the code generating means generates PN code having autocorrelation, and sequentially shifts a phase of the PN code by one bit so as to output the PN code in chronological order as the code.

7. The capacitance detecting circuit according to claim 1, wherein the code generating means sequentially generates Walsh orthogonal code having different orders of bit strings so as to output the Walsh orthogonal code in chronological order as the code.

8. The capacitance detecting circuit according to claim 5, wherein the column line group includes the number of column lines smaller than the number of bits of the code, and

the decoding computation means performs product sum computation by associating the column lines of the column line group with the bits at predetermined positions and by associating an imaginary column line with the remaining bit so as to decode the voltages corresponding to the capacitances at the intersections.

9. A fingerprint sensor comprising the capacitance detecting circuit set forth in claim 1.

10. A fingerprint sensor comprising the capacitance detecting circuit set forth in claim 4.

11. A fingerprint sensor comprising the capacitance detecting circuit set forth in claim 5.