Smart lock-in circuit for phase-locked loops

• US 20060158261A1
• Filed: 01/15/2005
• Published: 07/20/2006
• Est. Priority Date: 01/15/2005
• Status: Active Grant

• Current Assignee: Smart Semiconductor, LLC (Equitable IP Corporation)
• Original Assignee: ANA Semiconductor, Bang J. Yoon, Yeol Young Kim
• Inventors: Park, Sangbeom
• Granted Patent: US 7,224,233 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence
• CPC Class Codes: H03L 7/105 Resetting the controlled oscillator when its frequency is outside a predetermined limit
• CPC Class Codes: Y10S 331/02 Phase locked loop having lock indicating or detecting means

Abstract

The smart lock-in circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

Claims

1. A smart lock-in circuit for enabling any phase-locked loop to become locked according to schedule, comprising:

a feedback line connected with the output and input of the smart lock-in circuit and also coupled to the output of a filter;

a sensor for sensing a voltage at the output, comparing with the midpoint voltage of the sensor, and providing its output;

two stacked PMOS transistors connected between power supply and the output; and

two stacked NMOS transistors connected between the output and ground.

2. The circuit as recited in claim 1 wherein the sensor is a low-voltage sensor.

3. The circuit as recited in claim 2 wherein the low-voltage sensor'"'"'s output is coupled to the gate terminal of the upper PMOS transistor.

4. The circuit as recited in claim 1 wherein the sensor is a high-voltage sensor.

5. The circuit as recited in claim 4 wherein the high-voltage sensor'"'"'s output is coupled to the gate terminal of the lower NMOS transistor.

6. The circuit as recited in claim 1 wherein the sensor is both a low-voltage sensor and a high-voltage sensor.

7. The circuit as recited in claim 6 wherein the low-voltage sensor'"'"'s output is coupled to the gate terminal of the upper PMOS transistor and the high-voltage sensor'"'"'s output is coupled to the gate terminal of the lower NMOS transistor.

8. The circuit as recited in claim 1 wherein the sensor is an even number of inverters

9. The circuit as recited in claim 1 wherein the sensor is comparator.

10. The circuit as recited in claim 1 wherein the sensor is operational amplifier.

11. The circuit as recited in claim 1 wherein the sensor is an even number of NAND gates since the two-input CMOS NAND gate can be used as an enabling inverter with one input serving as an active high enable input and the other used as the logical input.

12. The circuit as recited in claim 1 wherein the sensor is an even number of NOR gates since the two-input CMOS NOR gate can be used as an enabling inverter with one input serving as an active low enable input and the other used as the logical input.

13. The circuit as recited in claim 1 further comprising a power-down NMOS transistor so that no current flows into the circuit during power-down mode.

14. The circuit as recited in claim 13 wherein the output of the smart lock-in circuit is coupled to the output of the filter connected between the output and ground.

15. The circuit as recited in claim 13 wherein the output of the smart lock-in circuit is at ground when the power-down input is at the power supply.

16. The circuit as recited in claim 1 further comprising a power-down PMOS transistor and a power-down inverter so that no current flows into the circuit during power-down mode.

17. The circuit as recited in claim 16 wherein the output of the smart lock-in circuit is coupled to the output of the filter connected between the output and power supply.

18. The circuit as recited in claim 16 wherein the output of the smart lock-in circuit is at power supply when the power-down input is at the power supply.

19. The circuit as recited in claim 16 wherein a power-down inverter is an odd number of inverters.

20. The circuit as recited in claim 1 wherein the smart lock-in circuit is applied to all phase-locked loops without regard to architectures, topologies, and schematics.