Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces

• US 20060158917A1
• Filed: 01/14/2005
• Published: 07/20/2006
• Est. Priority Date: 01/14/2005
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bartley, Gerald Keith, Hovis, William Paul, Borkenhagen, John Michael, Rudrud, Paul
• Granted Patent: US 7,468,993 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner.

Claims

1. A solid state memory device, comprising:

a plurality of memory arrays;

a plurality of data interconnects, each data interconnect dedicated to one of the plurality of memory arrays;

a plurality of read multiplexers, each including an output coupled to one of the plurality of data interconnects and a plurality of inputs configured to be selectively routed to the output responsive to a select signal, each of the plurality of inputs coupled to one of the plurality of memory arrays;

a plurality of write multiplexers, each including an output coupled to one of the plurality of memory arrays and a plurality of inputs configured to be selectively routed to the output responsive to a select signal, each of the plurality of inputs coupled to one of the plurality of data interconnects; and

control logic configured to apply select signals to the plurality of read and write multiplexers to configure the plurality of read and write multiplexers to operate in one of a normal mode and a safe mode, wherein in the normal mode, the control logic configures each read and write multiplexer to couple each of the plurality of data interconnects to the memory array to which such data interconnect is dedicated, and in the safe mode, the control logic configures each read and write multiplexer to time multiplex and replicate data associated with each of the plurality of memory arrays over each of at least a subset of the data interconnects.

2. A circuit arrangement, comprising:

a plurality of interfaces, each interface configured to communicate data associated with a respective logic circuit among a plurality of logic circuits such that data associated with the plurality of logic circuits is communicated in parallel by the plurality of interfaces; and

control logic coupled to the plurality of interfaces and configured to dynamically reconfigure the plurality of interfaces to time multiplex and replicate data associated with each of the plurality of logic circuits over each of at least a subset of the plurality of interfaces.

3. The circuit arrangement of claim 2, wherein each interface is dedicated to the respective logic circuit with which the interface is associated when not dynamically reconfigured by the control logic.

4. The circuit arrangement of claim 2, wherein each logic circuit comprises a memory array, and wherein each interface comprises a data interconnect.

5. The circuit arrangement of claim 4, further comprising selection logic configured to select valid data from the replicated data communicated by the plurality of interfaces.

6. The circuit arrangement of claim 5, wherein the selection logic is configured to select the valid data according to a voting protocol.

7. The circuit arrangement of claim 6, wherein the selection logic is configured to selectively ignore a known failed interface when selecting valid data from the replicated data.

8. The circuit arrangement of claim 4, further comprising test logic configured to communicate deterministic data patterns over the plurality of interfaces to identify a failed interface.

9. The circuit arrangement of claim 4, further comprising:

a plurality of read multiplexers, each including an output coupled to one of the plurality of data interconnects and a plurality of inputs configured to be selectively routed to the output responsive to a select signal, each of the plurality of inputs coupled to one of the plurality of memory arrays; and

a plurality of write multiplexers, each including an output coupled to one of the plurality of memory arrays and a plurality of inputs configured to be selectively routed to the output responsive to a select signal, each of the plurality of inputs coupled to one of the plurality of data interconnects;

wherein the control logic is configured to dynamically reconfigure the plurality of interfaces by controlling the read and write multiplexers via the select signals.

10. The circuit arrangement of claim 4, wherein the plurality of interfaces and the control logic are logically arranged in a first grouping, the circuit arrangement further comprising a second grouping including a second plurality of interfaces and second control logic configured to dynamically reconfigure the second plurality of interfaces.

11. The circuit arrangement of claim 2, wherein each logic circuit comprises a memory array, and wherein the control logic is disposed on a separate integrated circuit device from the plurality of memory arrays.

12. The circuit arrangement of claim 2, wherein each logic circuit comprises a memory array, and wherein the control logic is disposed on the same integrated circuit device as the plurality of memory arrays.

13. An apparatus comprising:

a plurality of integrated circuit devices, each comprising a plurality of memory arrays and the circuit arrangement of claim 2;

and

a memory controller coupled to the plurality of integrated circuit devices and configured to initiate dynamic reconfiguration of the plurality of interfaces by the control logic on each integrated circuit device.

14. A program product, comprising a hardware definition program that defines the circuit arrangement of claim 2;

and a computer readable signal bearing medium bearing the hardware definition program, wherein the signal bearing medium includes at least one of a transmission type media and a recordable media.

15. A circuit arrangement configured for use with a plurality of interfaces, each of which configured to communicate data associated with a respective logic circuit among a plurality of logic circuits such that data associated with the plurality of logic circuits is communicated in parallel by the plurality of interfaces, the circuit arrangement comprising:

control logic configured to initiate dynamic reconfiguration of the plurality of interfaces to time multiplex and replicate data associated with each of the plurality of logic circuits over each of at least a subset of the plurality of interfaces; and

selection logic coupled to the control logic and configured to receive replicated data over the plurality of interfaces and select valid data therefrom.

16. The circuit arrangement of claim 15, wherein the selection logic is configured to select valid data from the replicated data according to a voting protocol.

17. The circuit arrangement of claim 16, wherein the selection logic is configured to selectively ignore a known failed interface when selecting valid data from the replicated data.

18. The circuit arrangement of claim 15, wherein the control logic and the selection logic are disposed in a solid state memory device.

19. The circuit arrangement of claim 15, wherein the control logic and the selection logic are disposed in a memory controller.

20. A method of communicating data over a plurality of interfaces, wherein each interface is configured to communicate data associated with a respective logic circuit among a plurality of logic circuits, the method comprising:

communicating data associated with the plurality of logic circuits in parallel over the plurality of interfaces; and

dynamically reconfiguring the plurality of interfaces to time multiplex and replicate data associated with each of the plurality of logic circuits over each of at least a subset of the plurality of interfaces.

21. The method of claim 20, wherein each interface is dedicated to the respective logic circuit with which the interface is associated prior to being dynamically reconfigured.

22. The method of claim 20, wherein each logic circuit comprises a memory array, and wherein each interface comprises a data interconnect.

23. The method of claim 22, further comprising selecting valid data from the replicated data communicated by the plurality of interfaces.

24. The method of claim 23, wherein selecting the valid data includes selecting the valid data according to a voting protocol.

25. The method of claim 24, wherein selecting the valid data includes selectively ignoring a known failed interface.

26. The method of claim 22, further comprising communicating deterministic data patterns over the plurality of interfaces to identify a failed interface.