Data path having grounded precharge operation and test compression capability

• US 20060158944A1
• Filed: 03/03/2006
• Published: 07/20/2006
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Chulmin Jung, George Raad
• Inventors: Jung, Chulmin, Raad, George
• Granted Patent: US 7,170,806 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Claims

1-6. -6. (canceled)

7. A data path for coupling data between a memory cell and an input/output (IO) sense amplifier, the data path comprising:

a first pair of data signal lines coupled to a first column of memory including a first memory cell during a memory read operation to the first memory cell;

a second pair of data signal lines coupled to a second column of memory including a second memory cell during a memory read operation to the second memory cell;

a third pair of data signal lines coupled to an input of the IO line sense amplifier;

first and second IO line coupling circuits coupled to the first and second data signal lines, respectively, each coupling circuit further coupled to the third pair of data signal lines and operable for a memory read operation to couple and decouple each of the signal lines of the third pair to and from a voltage supply in accordance with voltage levels of the signal lines of the first pair or the voltage levels of the signal lines of the second pair, the first and second coupling circuits operable in a test mode to couple and decouple each of the signal lines of the third pair to and from the voltage supply in accordance with voltage levels of the signal lines of the first pair and the signal lines of the second pair; and

a test compression circuit coupled to the third pair of data signal lines operable in the test mode to compare voltage levels of each of the signal lines to a reference voltage and in response, generate an output test signal indicative of whether the voltage levels of the signal lines of the third pair relative to the reference voltage are complementary or the same.

8. The data path of claim 7, further comprising a precharge circuit coupled to the third pair of data signal lines and operable to couple the third pair of data signal lines to ground to precharge the signal lines prior to a memory read operation.

9. The data path of claim 7, further comprising first and second data signal line precharge circuits coupled to a respective pair of data signal lines, each data signal line precharge circuit operable to couple the respective data signal lines to an internal voltage supply.

10. The data path of claim 7 wherein the third data signal lines comprise global input/output (GIO) signal lines and the first and second data signal lines comprise local input/output (LIO) signal lines, the GIO signal lines having greater inherent capacitance than the LIO signal lines.

11. The data path of claim 7 wherein the IO coupling circuit comprises:

a pair of p-channel MOS transistors, each having a source coupled to the voltage supply and a drain, each p-channel MOS transistor further having a gate coupled to receive a read activation signal; and

a pair of n-channel MOS transistors, each having a drain coupled to the drain of a respective one of the p-channel MOS transistors and having a source coupled to a respective one of the third data signal lines, each n-channel MOS transistor further having a gate coupled to a respective one of the first data signal lines.

12. The data path of claim 11 wherein the IO coupling circuit further comprises a pair of write n-channel MOS transistors each having a drain coupled to a respective one of the third pair data signal lines and a source coupled to a respective one of the first signal lines, and further having a gate coupled to receive a write activation signal.

13. The data path of claim 7 wherein the test compression circuit comprises:

first and second voltage comparison circuits, each voltage comparison circuit coupled to a respective one of the data signal lines of the third pair and having differential amplifier having a first input coupled to the respective data signal line and a second input coupled to a reference voltage supply, each voltage comparison circuit having an amplifier stage coupled to the differential amplifier stage to amplify the voltage difference between the voltage level of the data signal line to which the differential amplifier stage is coupled and the reference voltage and further having an output stage to provide output signals indicative of the amplified voltage difference; and

a logic circuit coupled to the output stages of the first and second voltage comparison circuits operable to compare the output signals of the first and second voltage comparison circuits and generate in response test compression signals indicative of whether the voltage levels of the data signal lines of the third pair are complementary or the same.

14. The data path of claim 13 wherein the output stage of each voltage comparison circuit comprises a two NAND gate set-reset latch.

15-20. -20. (canceled)

21. A memory device, comprising:

an address bus;

a control bus;

an address decoder coupled to the address bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder and control circuit

a read/write circuit coupled to the memory-cell array;

an output data buffer; and

a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) sense amplifier, the data path comprising;

a first pair of data signal lines coupled to a first column of memory including a first memory cell during a memory read operation to the first memory cell;

a second pair of data signal lines coupled to a second column of memory including a second memory cell during a memory read operation to the second memory cell;

a third pair of data signal lines coupled to an input of the IO line sense amplifier;

first and second IO line coupling circuits coupled to the first and second data signal lines, respectively, each coupling circuit further coupled to the third pair of data signal lines and operable for a memory read operation to couple and decouple each of the signal lines of the third pair to and from a voltage supply in accordance with voltage levels of the signal lines of the first pair or the voltage levels of the signal lines of the second pair, the first and second coupling circuits operable in a test mode to couple and decouple each of the signal lines of the third pair to and from the voltage supply in accordance with voltage levels of the signal lines of the first pair and the signal lines of the second pair; and

a test compression circuit coupled to the third pair of data signal lines operable in the test mode to compare voltage levels of each of the signal lines to a reference voltage and in response, generate an output test signal indicative of whether the voltage levels of the signal lines of the third pair relative to the reference voltage are complementary or the same.

22. The memory device of claim 21 wherein the data path further comprises a precharge circuit coupled to the third pair of data signal lines and operable to couple the third pair of data signal lines to ground to precharge the signal lines prior to a memory read operation.

23. The memory device of claim 21 wherein the data path further comprises first and second data signal line precharge circuits coupled to a respective pair of data signal lines, each data signal line precharge circuit operable to couple the respective data signal lines to an internal voltage supply.

24. The memory device of claim 21 wherein the third data signal lines of the data path comprise global input/output (GIO) signal lines and the first and second data signal lines comprise local input/output (LIO) signal lines, the GIO signal lines having greater inherent capacitance than the LIO signal lines.

25. The memory device of claim 21 wherein the IO coupling circuit of the data path comprises:

a pair of p-channel MOS transistors, each having a source coupled to the voltage supply and a drain, each p-channel MOS transistor further having a gate coupled to receive a read activation signal; and

a pair of n-channel MOS transistors, each having a drain coupled to the drain of a respective one of the p-channel MOS transistors and having a source coupled to a respective one of the third data signal lines, each n-channel MOS transistor further having a gate coupled to a respective one of the first data signal lines.

26. The memory device of claim 25 wherein the IO coupling circuit further comprises a pair of write n-channel MOS transistors each having a drain coupled to a respective one of the third pair data signal lines and a source coupled to a respective one of the first signal lines, and further having a gate coupled to receive a write activation signal.

27. The memory device of claim 21 wherein the test compression circuit of the data path comprises:

first and second voltage comparison circuits, each voltage comparison circuit coupled to a respective one of the data signal lines of the third pair and having differential amplifier having a first input coupled to the respective data signal line and a second input coupled to a reference voltage supply, each voltage comparison circuit having an amplifier stage coupled to the differential amplifier stage to amplify the voltage difference between the voltage level of the data signal line to which the differential amplifier stage is coupled and the reference voltage and further having an output stage to provide output signals indicative of the amplified voltage difference; and

a logic circuit coupled to the output stages of the first and second voltage comparison circuits operable to compare the output signals of the first and second voltage comparison circuits and generate in response test compression signals indicative of whether the voltage levels of the data signal lines of the third pair are complementary or the same.

28. The memory device of claim 27 wherein the output stage of each voltage comparison circuit comprises a two NAND gate set-reset latch.

29-34. -34. (canceled)

35. A processor-based system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and output devices; and

a memory device coupled to the processor, the memory device comprising;

an address bus;

a control bus;

an address decoder coupled to the address bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder and control circuit

a read/write circuit coupled to the memory-cell array;

an output data buffer; and

a data path coupled to a read/write circuit and the output data buffer for coupling data between a memory cell and an input/output (IO) sense amplifier, the data path comprising;

a first pair of data signal lines coupled to a first column of memory including a first memory cell during a memory read operation to the first memory cell;

a second pair of data signal lines coupled to a second column of memory including a second memory cell during a memory read operation to the second memory cell;

a third pair of data signal lines coupled to an input of the IO line sense amplifier;

first and second IO line coupling circuits coupled to the first and second data signal lines, respectively, each coupling circuit further coupled to the third pair of data signal lines and operable for a memory read operation to couple and decouple each of the signal lines of the third pair to and from a voltage supply in accordance with voltage levels of the signal lines of the first pair or the voltage levels of the signal lines of the second pair, the first and second coupling circuits operable in a test mode to couple and decouple each of the signal lines of the third pair to and from the voltage supply in accordance with voltage levels of the signal lines of the first pair and the signal lines of the second pair; and

a test compression circuit coupled to the third pair of data signal lines operable in the test mode to compare voltage levels of each of the signal lines to a reference voltage and in response, generate an output test signal indicative of whether the voltage levels of the signal lines of the third pair relative to the reference voltage are complementary or the same.

36. The process-based system of claim 35 wherein the data path further comprises a precharge circuit coupled to the third pair of data signal lines and operable to couple the third pair of data signal lines to ground to precharge the signal lines prior to a memory read operation.

37. The process-based system of claim 35 wherein the data path further comprises first and second data signal line precharge circuits coupled to a respective pair of data signal lines, each data signal line precharge circuit operable to couple the respective data signal lines to an internal voltage supply.

38. The process-based system of claim 35 wherein the third data signal lines of the data path comprise global input/output (GIO) signal lines and the first and second data signal lines comprise local input/output (LIO) signal lines, the GIO signal lines having greater inherent capacitance than the LIO signal lines.

39. The process-based system of claim 35 wherein the IO coupling circuit of the data path comprises:

a pair of p-channel MOS transistors, each having a source coupled to the voltage supply and a drain, each p-channel MOS transistor further having a gate coupled to receive a read activation signal; and

a pair of n-channel MOS transistors, each having a drain coupled to the drain of a respective one of the p-channel MOS transistors and having a source coupled to a respective one of the third data signal lines, each n-channel MOS transistor further having a gate coupled to a respective one of the first data signal lines.

40. The process-based system of claim 39 wherein the IO coupling circuit further comprises a pair of write n-channel MOS transistors each having a drain coupled to a respective one of the third pair data signal lines and a source coupled to a respective one of the first signal lines, and further having a gate coupled to receive a write activation signal.

41. The process-based system of claim 35 wherein the test compression circuit of the data path comprises:

first and second voltage comparison circuits, each voltage comparison circuit coupled to a respective one of the data signal lines of the third pair and having differential amplifier having a first input coupled to the respective data signal line and a second input coupled to a reference voltage supply, each voltage comparison circuit having an amplifier stage coupled to the differential amplifier stage to amplify the voltage difference between the voltage level of the data signal line to which the differential amplifier stage is coupled and the reference voltage and further having an output stage to provide output signals indicative of the amplified voltage difference; and

a logic circuit coupled to the output stages of the first and second voltage comparison circuits operable to compare the output signals of the first and second voltage comparison circuits and generate in response test compression signals indicative of whether the voltage levels of the data signal lines of the third pair are complementary or the same.

42. The process-based system of claim 41 wherein the output stage of each voltage comparison circuit comprises a two NAND gate set-reset latch.

43-45. -45. (canceled)

46. A method for testing memory cells of a memory array, comprising:

coupling a pair of global data signal lines to a voltage supply through a plurality of switches;

coupling data of a plurality of memory cells to a respective one of a plurality of local data signal lines, the local data signal lines coupled to a respective one of the plurality of switches;

for each of the plurality of local data signal lines, decoupling one of the pair of global data signal lines from the voltage supply based on the data of the respective memory cell coupled to the respective local data signal lines;

comparing the voltage levels of each global data signal line to a reference voltage; and

generating an output signal having a logic level indicative of whether the data coupled to the respective local data signal lines matches expected data based on whether the voltage level of each global data signal line relative to the reference voltage is the same or different.

47. The method of claim 46 wherein generating an output signal having a logic level indicative of whether the data coupled to the respective local data signal lines matches expected data based on whether the voltage level of each global data signal line relative to the reference voltage is the same or different comprises generating the output signal having a first logic level indicative of data matching in response to the voltage levels of the global data signal lines relative to the reference voltage are different and generating the output signal having a second logic level indicative of at least one data mismatch in response to the voltage levels of the global data signal lines relative to the reference voltage are the same.

48. The method of claim 46, further comprising:

precharging the global data signal lines to ground; and

precharging the local data signal lines to an internal voltage level.