Memory device
First Claim
1. A memory device comprising:
- a plurality of bit lines and a plurality of word lines;
a plurality of memory cells, each of said memory cells provided at an intersection of an associated bit line and an associated word line, each of said memory cells including a programmable resistance element; and
a control circuit for performing control to carry out a refresh operation of said memory cell responsive to a change in a resistance value of said memory cell.
1 Assignment
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Accused Products
Abstract
Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.
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Citations
26 Claims
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1. A memory device comprising:
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a plurality of bit lines and a plurality of word lines;
a plurality of memory cells, each of said memory cells provided at an intersection of an associated bit line and an associated word line, each of said memory cells including a programmable resistance element; and
a control circuit for performing control to carry out a refresh operation of said memory cell responsive to a change in a resistance value of said memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A memory device having a plurality of memory cells, each including a phase change device, said memory device comprising:
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a dummy cell including a phase change device, said dummy cell being subjected to a stress in accordance with the number of times of read and write operations;
a circuit for detecting a change in a resistance value of the phase change device of said dummy cell; and
refresh requesting means for issuing a refresh request when the resistance value of said phase change device in said dummy cell has been changed beyond a predetermined reference value;
said memory cell and the dummy cell being refreshed based on said refresh request. - View Dependent Claims (24)
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23. A memory device having a plurality of memory cells, each including a phase change device, said memory device comprising:
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a counter for counting the number of times of read; and
means for monitoring the number of times of read and for issuing a refresh request when the number of times of read has reached a preset value.
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25. A memory device having a plurality of memory cells, each including a phase change device, said memory device comprising:
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first and second reference current circuits for supplying first and second reference currents, corresponding to first and second states, respectively; and
refresh requesting means for comparing the currents flowing through said memory cells to said first and second reference currents and for issuing a refresh request when a predetermined offset has been produced;
said memory cells being refreshed based on said refresh request. - View Dependent Claims (26)
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Specification