Substrate having silicon germanium material and stressed silicon nitride layer

• US 20060160314A1
• Filed: 01/15/2005
• Published: 07/20/2006
• Est. Priority Date: 01/15/2005
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Arghavani, Reza
• Granted Patent: US 7,323,391 B2
• Time in Patent Office: Days
• US Class Current: 438/285
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

(a) forming a doped silicon region on a substrate;

(b) forming on the substrate, a silicon germanium material adjacent to the doped silicon region to induce a stress in the doped silicon region; and

(c) forming on the substrate, a stressed silicon nitride layer over at least a portion of the doped silicon region to further stress the doped silicon region.

2. A method according to claim 1 wherein (b) comprises epitaxially growing silicon germanium material on the substrate, the silicon germanium material having the chemical stoichiometry of Si_1-xGe_x, where x is from about 0.15 to about 0.3.

3. A method according to claim 1 wherein (b) comprises forming silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is selected to induce a stress of at least about 1 GPa in the doped silicon region.

4. A method according to claim 1 wherein (b) comprises forming a transistor having at least one of a source and a drain region that comprises the silicon germanium material.

5. A method according to claim 1 wherein (c) comprises forming a stressed silicon nitride layer comprising a compressive stress having an absolute value of at least about 2.5 GPa.

6. A method according to claim 1 wherein (c) comprises forming a stressed silicon nitride layer comprising a tensile stress of at least about 1.5 GPa.

7. A method according to claim 6 further comprising forming a stressed dielectric layer over at least a portion of the stressed silicon nitride layer, the stressed dielectric layer having a tensile stress of at least about 200 MPa.

8. A method according to claim 6 further comprising forming a stressed silicon oxide layer adjacent the silicon germanium material, the stressed silicon oxide layer having a tensile stress of at least about 800 MPa.

9. A method according to claim 1 further comprising forming a stressed metal silicide layer over at least a portion of the silicon germanium material.

10. A semiconductor device fabricated according to the method of claim 1.

18. A method according to claim 1 further comprising forming a stressed metal silicide layer over at least a portion of the source and drain regions.

11. A method of fabricating a semiconductor device, the method comprising:

(a) forming a transistor on a substrate by;

(i) forming a source region and a drain region on the substrate, each of the source and drain regions comprising silicon germanium material; and

(ii) forming a channel region configured to conduct charge between the source region and drain region, the channel region comprising doped silicon, whereby stress is induced in the channel region by the silicon germanium material in the source and drain regions; and

(b) forming a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region,

whereby the silicon germanium material and the overlying stressed silicon nitride layer induce stress in the channel region that increases the carrier mobility of channel region.

12. A method according to claim 11 wherein (a) comprises epitaxially growing the silicon germanium in the source and drain regions, the silicon germanium material having the chemical stoichiometry of Si_1-xGe_x, where x is from about 0.15 to about 0.3.

13. A method according to claim 11 wherein (a) comprises forming source and drain regions comprising silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is selected to induce a stress of at least about 1 Pa in the channel region.

14. A method according to claim 11 wherein (b) comprises depositing a layer of silicon nitride by a chemical vapor deposition method having deposition parameters selected to deposit a layer of silicon nitride having a compressive stress having an absolute value of at least about 2.5 GPa.

15. A method according to claim 11 wherein (b) comprises depositing a layer of silicon nitride by a chemical vapor deposition method having deposition parameters selected to deposit a layer of silicon nitride having a tensile stress of at least about 1.5 GPa.

16. A method according to claim 11 further comprising forming a stressed dielectric layer over at least a portion of the stressed silicon nitride layer, the stressed dielectric layer having a tensile stress of at least about 200 MPa.

17. A method according to claim 11 further comprising forming a stressed silicon oxide layer adjacent the drain and source regions, the stressed silicon oxide layer having a tensile stress of at least about 800 MPa.

19. A semiconductor device comprising:

(a) a transistor comprising;

(i) source and drain regions comprising silicon germanium material; and

(ii) a channel region configured to conduct charge between the source and drain regions, the channel region comprising doped silicon, whereby stress is induced in the channel region by the silicon germanium material; and

(b) a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region,

whereby the silicon germanium material and the overlying stressed silicon nitride layer induce stress in the channel region that increase the carrier mobility of the channel region.

20. A device according to claim 19 wherein the source and drain regions comprise epitaxially grown silicon germanium material, the silicon germanium material having the chemical stoichiometry of Si_1-xGe_x, where x is from about 0.15 to about 0.3.

21. A device according to claim 19 wherein the source and drain regions comprise silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is selected to induce a stress of at least about 1 GPa in the channel region.

22. A device according to claim 19 wherein the stressed silicon nitride layer comprises a compressive stress having an absolute value of at least about 2.5 GPa.

23. A device according to claim 19 wherein the stressed silicon nitride layer comprises a tensile stress at least about 1.5 GPa.

24. A device according to claim 23 further comprising a stressed dielectric layer over at least a portion of the stressed silicon nitride layer, the stressed dielectric layer having a tensile stress of at least about at least about 200 MPa.

25. A device according to claim 23 further comprising a stressed silicon oxide layer adjacent the drain and source regions, the stressed silicon oxide layer having a tensile stress of at least about 800 MPa.

26. A device according to claim 19 further comprising a stressed metal silicide layer over at least a portion of the source and drain regions.

27. A method of fabricating a semiconductor device, the method comprising:

(a) forming a transistor on a substrate by;

(i) forming a source region and a drain region on the substrate, each of the source and drain regions comprising silicon germanium material; and

(ii) forming a channel region configured to conduct charge between the source region and drain region, the channel region comprising germanium, whereby stress is induced in the channel region by the silicon germanium material in the source and drain regions; and

(b) forming a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region,

whereby the silicon germanium material and the overlying stressed silicon nitride layer induce stress in the channel region that increases the carrier mobility of channel region.

28. A semiconductor device comprising:

(a) a transistor comprising;

(i) source and drain regions comprising silicon germanium material; and

(ii) a channel region configured to conduct charge between the source and drain regions, the channel region comprising germanium, whereby stress is induced in the channel region by the silicon germanium material; and

(b) a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region,

whereby the silicon germanium material and the overlying stressed silicon nitride layer induce stress in the channel region that increase the carrier mobility of the channel region.