Method of fabricating a semiconductor device

• US 20060160320A1
• Filed: 12/13/2005
• Published: 07/20/2006
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsuchitani, Masanobu, Kawamura, Keiko, Shinohara, Hitoshi
• Granted Patent: US 7,507,630 B2
• Time in Patent Office: Days
• US Class Current: 438/401
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film; selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern; selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and burying gate material in the trench to form the trench gate.

Claims

1. A method of fabricating a semiconductor device with a semiconductor body and a trench gate formed in a cell area thereof, comprising:

forming an insulating film on the semiconductor body to cover a termination area surrounding the cell area;

forming a mask material film to cover the cell area and the insulating film;

forming a resist film to cover the mask material film;

patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film;

selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern;

selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and

burying gate material in the trench to form the trench gate.

2. The method according to claim 1, wherein

the gate-use resist pattern is formed to have a stripe-shaped resist pattern and a frame-shaped resist pattern surrounding it.

3. The method according to claim 2, wherein the dummy resist pattern is formed to surround the frame-shaped resist pattern.

4. The method according to claim 2, wherein the gate-use resist pattern is formed to have a plurality of stripe-shaped resist patterns, and

the dummy resist pattern is formed apart from the frame-shaped resist pattern with a distance substantially equal to each gap in the stripe-shaped resist patterns and a gap between the frame-shaped resist pattern and the stripe-shaped resist pattern disposed adjacent thereto.

5. The method according to claim 1, wherein

the insulating film serves as a field insulating film, and the mask material film is formed of a CVD silicon oxide film.

6. The method according to claim 1, wherein

the semiconductor device is a transistor,

the semiconductor body comprises a semiconductor substrate serving as a first main electrode region;

an epitaxial layer of a first conductivity type formed thereon; and

a base region of a second conductivity type formed on the epitaxial layer, and

the trench gate is formed to extend into the semiconductor body from the surface of the semiconductor body so as to reach the bottom of the base region, a second main electrode region of the first conductivity type being formed on the surface of the base region.

7. A method of fabricating a semiconductor device comprising:

forming an underlying material film on or above a semiconductor body, on or over a first area of which a certain pattern is to be formed, to cover a second area adjacent to the first area;

forming a patterning object film above the first area and the second area, on or above which the underlying material film is formed, of the semiconductor body;

forming a resist film on the patterning object film to cover it;

patterning the resist film to have an opening above the first area, which serves as a certain resist pattern corresponding to the certain pattern, and another opening above the second area, which serves as a dummy resist pattern, in such a manner that the dummy resist pattern surrounds the certain resist pattern or at least two portions thereof are extended in the elongated direction of the certain resist pattern and disposed on the both side of the certain resist pattern;

selectively etching the patterning object film by use of the patterned resist film as a mask to form the certain pattern in such a manner that the underlying material film is remained under the dummy resist pattern.

8. The method according to claim 7, wherein

the patterning object film is formed of the same material as the underlying material film to be thinner than the underlying material film.

9. The method according to claim 7, wherein

the certain resist pattern is a first stripe pattern;

and the dummy resist pattern is formed of two second stripe patterns sandwiching the first stripe pattern.

10. The method according to claim 7, wherein

the dummy resist pattern is formed to surround the certain resist pattern.

11. The method according to claim 7, further comprising:

selectively etching the semiconductor body by use of the patterning object film, in which the certain pattern is formed, as another mask to form a trench therein.

12. The method according to claim 7, wherein

a power transistor cell is formed on the semiconductor body, and

the patterning object film is an interlayer insulating film formed to cover the power transistor cell, in which a contact hole is formed as the certain pattern.

13. The method according to claim 12, further comprising:

burying metal material in the contact hole to form a main electrode of the power transistor cell.

14. A method of fabricating a semiconductor device comprising:

forming a patterning object film and an etching resistant material film, the etching rate of which is lower than the patterning object film, on or above a semiconductor body to cover a first area on or over which a certain pattern is to be formed and a second area adjacent to the first area, respectively;

forming a resist film on the patterning object film and the etching resistant material film to cover them;

patterning the resist film to have an opening above the first area, which serves as a certain resist pattern corresponding to the certain pattern, and another opening above the second area, which serves as a dummy resist pattern, in such a manner that the dummy resist pattern surrounds the certain resist pattern or at least two portions thereof are extended in the elongated direction of the certain resist pattern and disposed on the both side of the certain resist pattern;

selectively etching the patterning object film by use of the patterned resist film as a mask to form the certain pattern in such a manner that the etching resistant material film is remained under the dummy resist pattern.

15. The method according to claim 14, wherein

the patterning object film and the etching resistant material film are formed with substantially the same thickness.

16. The method according to claim 14, wherein

the certain resist pattern is a first stripe pattern;

and the dummy resist pattern is formed of two second stripe patterns sandwiching the first stripe pattern.

17. The method according to claim 14, wherein

the dummy resist pattern is formed to surround the certain resist pattern.

18. The method according to claim 14, further comprising:

selectively etching the semiconductor body by use of the patterning object film, in which the certain pattern is formed, as another mask to form a trench therein.

19. The method according to claim 14, wherein

a power transistor cell is formed on the semiconductor body, and

the patterning object film is an interlayer insulating film formed to cover the power transistor cell, in which a contact hole is formed as the certain pattern.

20. The method according to claim 19, further comprising:

burying metal material in the contact hole to form a main electrode of the power transistor cell.