Software emulation of directed exceptions in a multithreading processor
First Claim
1. A method for performing software emulation of a directed exception in a multithreading processor running a multiprocessor operating system, the processor having a plurality of thread contexts each comprising storage elements that describe a state of execution of a respective plurality of threads running on the respective plurality of thread contexts, the method comprising:
- writing, by a first thread running on a first thread context, to a second thread context to cause a second thread running on the second thread context to stop running;
writing, by the first thread, to the second thread context an address of an exception handler of the operating system; and
writing, by the first thread, to the second thread context to cause the exception handler to commence running at the address on the second thread context.
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Accused Products
Abstract
A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a multiprocessor operating system. However, the microprocessor hardware does not support the ability for one TC to direct an exception to another TC, i.e., to specify to which of the other TCs the exception is directed. A first thread running on a first TC of the operating system executes architected instructions to halt a second thread (either user or kernel thread) running on a second TC, save state of the second TC, write the second TC state to emulate an exception—including writing a restart register with the address of an exception handler, and unhalt the second TC to execute the exception hander.
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Citations
70 Claims
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1. A method for performing software emulation of a directed exception in a multithreading processor running a multiprocessor operating system, the processor having a plurality of thread contexts each comprising storage elements that describe a state of execution of a respective plurality of threads running on the respective plurality of thread contexts, the method comprising:
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writing, by a first thread running on a first thread context, to a second thread context to cause a second thread running on the second thread context to stop running;
writing, by the first thread, to the second thread context an address of an exception handler of the operating system; and
writing, by the first thread, to the second thread context to cause the exception handler to commence running at the address on the second thread context. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A multiprocessor computer system, comprising:
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a microprocessor, comprising at least first and second thread contexts, each comprising;
a restart register; and
a control register, for controlling whether said thread context is halted from execution;
a memory, coupled to said microprocessor, for storing a first thread of execution for execution on said first thread context; and
a multiprocessing operating system (MP OS), stored in said memory, comprising a second thread of execution for execution on said second thread context configured;
to write to said control register of said first thread context to halt execution of said first thread;
to write to said restart register of said first thread context an address of an exception handler of said MP OS; and
to write to said control register of said first thread context to commence execution of said exception handler on said first thread context at said address. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66)
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67. A computer program product for use with a computing device, the computer program product comprising:
a computer usable medium, having computer readable program code embodied in said medium, for causing a method for performing software emulation of a directed exception in a multithreading processor running a multiprocessor operating system, the processor having a plurality of thread contexts each comprising storage elements that describe a state of execution of a respective plurality of threads running on the respective plurality of thread contexts, said computer readable program code comprising;
first program code for providing a step of writing, by a first thread running on a first thread context, to a second thread context to cause a second thread running on the second thread context to stop running;
second program code for providing a step of writing, by the first thread, to the second thread context an address of an exception handler of the operating system; and
third program code for providing a step of writing, by the first thread, to the second thread context to cause the exception handler to commence running at the address on the second thread context. - View Dependent Claims (68, 69)
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70. A method for providing operating system software for performing emulation of a directed exception in a multithreading processor running a multiprocessor operating system, the processor having a plurality of thread contexts each comprising storage elements that describe a state of execution of a respective plurality of threads running on the respective plurality of thread contexts, the method comprising:
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providing computer-readable program code describing the operating system software, the program code comprising;
first program code for providing a step of writing, by a first thread running on a first thread context, to a second thread context to cause a second thread running on the second thread context to stop running;
second program code for providing a step of writing, by the first thread, to the second thread context an address of an exception handler of the operating system; and
third program code for providing a step of writing, by the first thread, to the second thread context to cause the exception handler to commence running at the address on the second thread context; and
transmitting the computer-readable program code as a computer data signal on a network.
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Specification