System and method for multimedia delivery in a wireless environment

• US 20060161675A1
• Filed: 01/20/2005
• Published: 07/20/2006
• Est. Priority Date: 01/20/2005
• Status: Active Grant

• Current Assignee: VIXS Systems Incorporated (Pixelworks Incorporated)
• Original Assignee: VIXS Systems Incorporated (Pixelworks Incorporated)
• Inventors: Doyle, James, Ducharme, Paul, Chiu, Adeline, Girardeau, James Jr.
• Granted Patent: US 7,421,048 B2
• Time in Patent Office: Days
• US Class Current: 709/231
• CPC Class Codes: H04N 21/23406 involving management of server-side video buffer
• CPC Class Codes: H04N 21/235 Processing of additional data, e.g. scrambling of additional data or processing content descriptors
• CPC Class Codes: H04N 21/2383 Channel coding or modulation of digital bit-stream, e.g. QPSK modulation arrangements for detecting or preventing errors in the information received by adapting the channel coding H04L1/0009; analogue front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/435 Processing of additional data, e.g. decrypting of additional data, reconstructing software from modules extracted from the transport stream
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/6332 directed to client
• CPC Class Codes: H04N 21/8547 involving timestamps for synchronizing content

Abstract

A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing device, synchronizing a first timing reference of the multimedia decoder to a second timing reference of the multimedia encoder, receiving, at a network interface of the first multimedia processing device, an encoded multimedia data stream from a network interface of the second multimedia processing device, wherein the encoded multimedia data stream is encoded by the multimedia encoder based on the second clock and the second timing reference, and decoding the encoded multimedia data stream at the multimedia decoder based on the first clock and the first timing reference.

Claims

1. A method comprising:

synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing device;

synchronizing a first timing reference of the multimedia decoder to a second timing reference of the multimedia encoder;

receiving, at a network interface of the first multimedia processing device, an encoded multimedia data stream from a network interface of the second multimedia processing device, wherein the encoded multimedia data stream is encoded by the multimedia encoder based on the second clock and the second timing reference; and

decoding the encoded multimedia data stream at the multimedia decoder based on the first clock and the first timing reference.

2. The method of claim 1, wherein synchronizing the first clock to the second clock includes:

receiving, at the first multimedia processing device, a first offset value representative of a frequency offset between the second clock and a third clock of the second multimedia processing device;

determining a second offset value representative of a frequency offset between the third clock and a fourth clock of the first multimedia processing device; and

adjusting the first clock based on the first offset value and the second offset value.

3. The method of claim 2, wherein the first clock is further adjusted based on an error value determined from a fullness of an input buffer to store the encoded multimedia data stream at the first multimedia processing device.

4. The method of claim 2, wherein the first clock drives the multimedia decoder, the second clock drives the multimedia encoder, the third clock drives the network interface of the second multimedia processing device and the fourth clock drives the network interface of the first multimedia processing device.

5. The method of claim 4, wherein the network interfaces comprise wireless transceivers.

6. The method of claim 5, wherein the wireless transceivers are compatible with IEEE 802.11.

7. The method of claim 4, wherein the network interfaces include PHY-based interfaces.

8. The method of claim 2, wherein the first offset value represents a difference between clock ticks of the first clock source and clock ticks of the second clock source over a predetermined time period.

9. The method of claim 1, wherein synchronizing the first timing reference of the multimedia decoder to the second timing reference of the multimedia encoder includes:

receiving, at the first multimedia device, a multimedia stream having a first plurality of timing references, the first plurality of timing references representing absolute timing references converted to relative timing references based on the second clock;

converting, at the first multimedia device, the first plurality of timing references from relative timing references to absolute timing references based on the first clock to generate a second plurality of timing references; and

synchronizing a numerically controlled oscillator (NCO) of the multimedia decoder based on at least a subset of the second plurality of timing references.

10. The method of claim 9, further comprising filtering an output of the NCO using a phase-locked loop (PLL).

11. The method of claim 9, wherein the multimedia stream includes an MPEG stream.

12. The method of claim 11, wherein the first plurality of timing references include primary reference clock (PRC) values or system reference clock (SRC) clock values.

13. The method of claim 1, wherein the encoded multimedia data stream comprises an MPEG stream.

14. The method of claim 1, wherein the multimedia encoder is an MPEG encoder and the multimedia decoder is an MPEG decoder.

15. The method of claim 1, wherein the network interfaces are wireless transceivers.

16. A method comprising:

determining, at a first multimedia processing device, a first offset between a first clock used to drive a multimedia encoder of the first multimedia processing device and a second clock used to drive a network interface of the first multimedia processing device;

encapsulating a value representative of the first offset in at least one packet; and

providing the at least one packet to a second multimedia processing device via the network interface of the first multimedia processing device.

17. The method of claim 16, wherein determining the first offset includes comparing a number of clock cycles of the first clock over a predetermined period with a number of clock cycles of the second clock over the predetermined period.

18. The method of claim 16, further comprising:

determining a second offset between the second clock and a third clock used to drive a network interface of a second multimedia processing device; and

adjusting a fourth clock used to drive a multimedia decoder of the second multimedia processing device based on the first and second offsets.

19. The method of claim 16, wherein the network interface comprises a wireless interface.

20. The method of claim 19, wherein the wireless interface is compatible with IEEE 802.11.

21. The method of claim 16, wherein the first offset represents a difference between clock ticks of the first clock and clock ticks of a second clock over a predetermined time period.

22. The method of claim 16, wherein the multimedia encoder comprises an MPEG encoder.

23. A system comprising:

a first multimedia processing device including;

a first clock having an output to provide a first clock signal;

a multimedia encoder having a first input operably coupled to the output of the first clock, a second input to receive multimedia data, and an output to provide an encoded multimedia stream, the multimedia encoder having a first timing reference;

a first network interface having a first input operably coupled to the output of the multimedia encoder and an output; and

a second multimedia processing device including;

a second network interface having a first input operably coupled to the output of the first network interface and an output;

a second clock having an output to provide a second clock signal;

a multimedia decoder having a first input operably coupled to the output of the second clock, a second input operably coupled to the output of the second network interface and an output to provide a decoded multimedia stream, the multimedia decoder having a second timing reference; and

a first synchronization module having a input operably coupled to the output of the second clock and an input operably coupled to the output of the second network interface and an output operably coupled to the second clock, the first synchronization module operable to;

synchronize the second clock to the first clock; and

synchronize the second timing reference to the first timing reference.

24. The system of claim 23, wherein the first multimedia processing device further comprises:

a third clock having an output operably coupled to a second input of the first network interface to provide a third clock signal;

a second synchronization module having a first input to receive the first clock signal and a second input to receive the third clock signal and an output to provide a first offset value representative of a frequency offset between the first clock and the third clock; and

wherein the network interface is operable to provide a packetized representation of the first offset value for transmission.

25. The system of claim 24, wherein the second multimedia processing device comprises a fourth clock having an output operably coupled to a second input of the second network interface, and wherein the first synchronization module is further operable to determine a second offset value representative of a frequency offset between the third clock and the fourth clock.

26. The system of claim 25, wherein the first synchronization module synchronizes the second clock to the first clock based on the first and second offset values.

27. The system of claim 26, wherein the second multimedia processing device further comprises an input buffer having an input operably coupled to the output of the second network interface, and wherein synchronization of the first clock to the second clock is further based on an error value determined from a fullness of the input buffer.

28. The system of claim 23, wherein first and second network interfaces comprise wireless interfaces.

29. The system of claim 28, wherein the wireless interfaces are compatible with IEEE 802.11.

30. A multimedia processing device comprising:

a first clock having an output to provide a first clock signal;

a second clock having an output to provide a second clock signal;

a network interface having a first input to receive a signal representative of an encoded multimedia data stream from a network and a second input operably coupled to the output of the first clock, the encoded multimedia data stream having a plurality of relative timing reference values;

a multimedia decoder having a first input operably coupled to the output of the second clock and a second input operably coupled to the network interface, the multimedia decoder to decode at least a portion of the multimedia data stream; and

a synchronization module having a first input operably coupled the output of the first clock, a second input operably coupled to the output of the second clock and a third input operably coupled to the network interface, the synchronization module operable to;

receive, from a second multimedia processing device, a first offset value representative of an offset between a third clock and fourth clock of the second multimedia processing device;

determine a second offset value representative of an offset between the first clock and the third clock;

adjust the second clock based on the first offset value and the second offset value; and

convert the relative timing reference values to absolute timing reference values based on the second clock.

31. The device of claim 30, further comprising an input buffer having an input operably coupled to the network interface and an output operably coupled to the second input of the multimedia decoder, and wherein the synchronization module is further adapted to adjust the second clock based on an error value determined from a fullness of the input buffer.

32. The device of claim 30, wherein the first offset value represents a difference between clock ticks of the third clock and clock ticks of the fourth clock over a predetermined time period and the second offset value represents a difference between clock ticks of the first clock and clock ticks of the second clock over a predetermined time period.

33. The device of claim 30, wherein the multimedia data stream includes an MPEG stream.

34. The device of claim 30, wherein the network interface includes a wireless interface.

35. The device of claim 34, wherein the wireless interface is compliant with IEEE 802.11.