Execution method and architecture of multiple-program-banks firmware

• US 20060161767A1
• Filed: 02/08/2005
• Published: 07/20/2006
• Est. Priority Date: 12/24/2004
• Status: Abandoned Application

• Current Assignee: Prolific Technology Inc.
• Original Assignee: Prolific Technology Inc.
• Inventors: Hung, Hunk, Lin, Chanson, Wang, Yu-Hsien
• Application Number:
  US11/052,084
• Publication Number:
  US 20060161767A1
• Time in Patent Office: Days
• US Class Current: 713/100
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

An execution method and architecture of multiple-program-banks firmware are proposed. The firmware is divided into multiple program banks stored in a nonvolatile memory. The program banks are also stored in a RAM. A No1 Bank manages the execution of these program banks. Programs of the program banks and updated codes of common programs can be modified at any time via an external interface bus. The execution method and architecture of multiple-program-banks firmware can accomplish better performance of program execution, and can change the content of a firmware program to enhance the flexibility of firmware.

Claims

1. An execution architecture of multiple-program-banks firmware used in an operational system having a microprocessor, said execution architecture of multiple-program-banks firmware comprising:

a common program ROM connected to said microprocessor and storing a firmware program;

a memory bank connected to said microprocessor and said common program ROM and capable of temporarily storing several instruction sets; and

a program bank storage device connected to said memory bank and having several program banks which store part of firmware program codes.

2. The execution architecture of multiple-program-banks firmware as claimed in claim 1, wherein said memory bank is an SRAM.

3. The execution architecture of multiple-program-banks firmware as claimed in claim 1, wherein execution actions of said firmware program include reading instruction, reading data and storing data.

4. The execution architecture of multiple-program-banks firmware as claimed in claim 1, wherein said firmware program has a program code of the main control flowchart.

5. The execution architecture of multiple-program-banks firmware as claimed in claim 1, wherein said storage device is a flash memory.

6. The execution architecture of multiple-program-banks firmware as claimed in claim 1 further comprising a common program RAM, which is connected to said common program ROM and can temporarily storing updated codes of said firmware program.

7. The execution architecture of multiple-program-banks firmware as claimed in claim 6, wherein said common program RAM is an SRAM.

8. The execution architecture of multiple-program-banks firmware as claimed in claim 6 further comprising a storage device, which is connected to said common program RAM and stores said updated codes.

9. The execution architecture of multiple-program-banks firmware as claimed in claim 1 further comprising a reset circuit, which is connected to said microprocessor and can reset said microprocessor.

10. An execution method of multiple-program-banks firmware comprising the steps of:

a microprocessor starting reading a firmware program stored in a common program ROM;

storing firmware program banks originally stored in a program storage device into a memory bank; and

said microprocessor executing said firmware.

11. The execution method of multiple-program-banks firmware as claimed in claim 10 further comprising the step of an external interface device storing modified program codes into said program storage device through said microprocessor.

12. The execution method of multiple-program-banks firmware as claimed in claim 10, wherein said program storage device is connected to said memory bank and has several program banks, and each said program bank is part program code of said firmware program.

13. The execution method of multiple-program-banks firmware as claimed in claim 10 further comprising the following steps before said microprocessor starts reading said firmware:

reading updated codes into a common program RAM and resetting said microprocessor if there are updated codes of said firmware stored in a storage device; and

continuing reading said firmware program if there are no updated codes.

14. The execution method of multiple-program-banks firmware as claimed in claim 13, wherein a reset circuit is connected to said microprocessor and can reset said microprocessor.

15. The execution method of multiple-program-banks firmware as claimed in claim 13 further comprising the step of reading said firmware program of said common program ROM and said updated codes of said common program RAM after resetting said microprocessor.

16. The execution method of multiple-program-banks firmware as claimed in claim 10, wherein said firmware program includes main execution program codes.

17. The execution method of multiple-program-banks firmware as claimed in claim 10, wherein execution actions of said firmware program include reading instruction, reading data and storing data.

18. The execution method of multiple-program-banks firmware as claimed in claim 10, wherein said firmware program banks has a No1 bank for managing execution of said firmware program banks.

19. An execution architecture of multiple-program-banks firmware used in an operational system having a microprocessor, said execution architecture of multiple-program-banks firmware comprising:

a common program RAM connected to said microprocessor and capable of temporarily storing several instruction sets;

a program bank storage device connected to said common program RAM and said microprocessor, said program bank storage device having a firmware program code; and

a program code check component connected to said common program RAM, said program bank storage device and said microprocessor.

20. The execution architecture of multiple-program-banks firmware as claimed in claim 19, wherein said common program RAM is an SRAM.

21. The execution architecture of multiple-program-banks firmware as claimed in claim 19, wherein said program bank storage device is a flash memory.

22. The execution architecture of multiple-program-banks firmware as claimed in claim 19, wherein said firmware program code includes common program codes, updated program codes and several program banks.

23. The execution architecture of multiple-program-banks firmware as claimed in claim 19, wherein said program code check component is an IC, which can determine whether said common program RAM has accessed said firmware program code.