PROTECTING SILICON GERMANIUM SIDEWALL WITH SILICON FOR STRAINED SILICON SILICON MOSFETS

• US 20060163608A1
• Filed: 04/06/2006
• Published: 07/27/2006
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: ZHU, Huilong, DORIS, Bruce B., MOCUTA, Dan M.
• Granted Patent: US 7,498,602 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

Claims

1. A semiconductor structure, comprising:

a substrate;

a raised source region on the substrate;

a raised drain region on the substrate; and

a first silicon layer over the raised source region and a second silicon layer over the raised drain region.

2. A semiconductor structure according to claim 1, wherein the substrate includes a SiGe layer atop a buried oxide layer.

3. A semiconductor structure according to claim 1, further comprising a gate stack on the substrate.

4. A semiconductor structure according to claim 3, further comprising a trench isolation surrounding the gate stack, source region and drain region.

5. A semiconductor structure according to claim 1, further comprising a a first silicide contact on the first silicon layer.

6. A semiconductor structure according to claim 1, further comprising a second silicide contact on the second silicon layer.

7. A semiconductor structure according to claim 1, wherein the first silicon layer is epitaxially formed silicon and the second silicon layer is epitaxially grown silicon.

8. A semiconductor structure according to claim 1, wherein the raised drain region is comprised of a strained silicon layer atop a SiGe layer

9. A semiconductor structure according to claim 8, wherein the strained silicon layer is comprised of epitaxially grown silicon.

10. A semiconductor structure according to claim 1, wherein the raised source region and the raised drain region are comprised of a strained silicon layer atop a SiGe layer.

11. A semiconductor structure according to claim 1, wherein the first silicon layer formed over the raised source region and the second silicon layer over the raised drain region include cap portions and sidewall portions, the semiconductor structure further comprising sacrificial spacers along the silicon sidewall portions.

12. A semiconductor structure according to claim 11, further comprising:

a third silicon layer over the cap of the first silicon layer over the raised source region; and

a fourth silicon layer over the cap of the second silicon layer over the raised drain region.

13. A semiconductor structure according to claim 12, wherein the sacrificial spacers have been removed.