Semiconductor device, and manufacturing method thereof

• US 20060163624A1
• Filed: 12/29/2005
• Published: 07/27/2006
• Est. Priority Date: 01/13/2005
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kuroi, Takashi
• Application Number:
  US11/319,740
• Publication Number:
  US 20060163624A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure

Abstract

The present invention provides a semiconductor device having a fully silicided gate electrode (full-silicide gate electrode) and a manufacturing method thereof, that has no problem of the increase in junction leak current, can increase a thickness of a metal silicide film formed on a source/drain region, and can form a fully silicided gate electrode and metal silicide film with one silicide forming process. A metal silicide film is formed such that its upper main face becomes higher than a semiconductor substrate. The thickness of the metal silicide film can be increased in order to secure a sufficient distance from an interface between the metal silicide film and the semiconductor substrate to an interface between a source/drain diffusion layer and the semiconductor substrate. As a result, the thickness of the metal silicide layer can be increased while avoiding the increase in junction leak current, even if a full-silicide gate electrode is formed.

Claims

1. A semiconductor device comprising:

a full-silicide gate electrode which is formed on a semiconductor substrate via a gate insulating film, and is fully silicided; and

a source/drain region which has an upper main face formed higher than said semiconductor substrate so as to sandwich said full-silicide gate electrode, wherein

said source/drain region includes a metal silicide film at least on the side of said upper main face.

2. The semiconductor device according to claim 1, wherein

said source/drain region further includes a source/drain diffusion layer formed on the surface of said semiconductor substrate so as to sandwich a channel region below said full-silicide gate electrode.

3. The semiconductor device according to claim 1, wherein

said source/drain region further includes a silicon germanium layer formed on the surface of said semiconductor substrate so as to sandwich a channel region below said full-silicide gate electrode.

4. The semiconductor device according to claim 1, wherein

said source/drain region is a Schottky source/drain formed of a metal silicide film effecting a Schottky junction with said semiconductor substrate.

5. The semiconductor device according to claim 1, wherein

the thickness of said metal silicide film is substantially equal to the thickness of said full-silicide gate electrode.

6. The semiconductor device according to claim 1, wherein

the thickness of said metal silicide film is smaller than the thickness of said full-silicide gate electrode.

7. The semiconductor device according to claim 6, wherein

said metal silicide film contains an element for suppressing silicidation.

8. The semiconductor device according to claim 1, wherein

the material of said metal silicide film is different between an N-type MISFET and a P-type MISFET.

9. The semiconductor device according to claim 1, wherein

said semiconductor substrate is an SOI substrate.

10. A manufacturing method of a semiconductor device comprising a full-silicide gate electrode which is formed on a semiconductor substrate via a gate insulating film and is fully silicided, and a source/drain region which has an upper main face formed higher than said semiconductor substrate so as to sandwich said full-silicide gate electrode, said source/drain region including a metal silicide film at least on the side of said upper main face,

the method comprising the steps of:

(a) forming a polysilicon gate electrode formed of a polysilicon film on said semiconductor substrate via said gate insulating film;

(b) forming a silicon film on said semiconductor substrate in said source/drain region;

(c) forming a metal film so as to cover said polysilicon gate electrode and said silicon film; and

(d) forming said full-silicide gate electrode and said metal silicide film by simultaneously siliciding said whole polysilicon gate electrode and a part of or whole of said silicon film.

11. The manufacturing method according to claim 10, further comprising the step of:

forming a source/drain diffusion layer on the surface of said semiconductor substrate in said source/drain region.

12. The manufacturing method according to claim 10, further comprising the step of:

forming a recess region on said semiconductor substrate in said source/drain region, wherein

said step (b) forms a silicon film containing germanium in said recess region.

13. The manufacturing method according to claim 10, wherein

said step (d) includes the step of siliciding said whole silicon film and, also, siliciding a part of said semiconductor substrate below said silicon film, thereby forming a Schottky source/drain.

14. The manufacturing method according to claim 10, wherein

said step (b) includes the step of forming said silicon film having a thickness substantially equal to the thickness of said polysilicon gate electrode.

15. The manufacturing method according to claim 10, wherein

said step (b) includes the step of forming said silicon film having a thickness smaller than the thickness of said polysilicon gate electrode.

16. The manufacturing method according to claim 15, further comprising the step of:

implanting an element for suppressing silicidation into said silicon film.

17. The manufacturing method according to claim 15, wherein

said step (b) includes the step of forming said silicon film while implanting an element for suppressing silicidation.

18. The manufacturing method according to claim 10, wherein

said step (c) includes the step of forming a first metal film on said N-type MISFET formation region, and the step of forming a second metal film on said P-type MISFET formation region.

19. The manufacturing method according to claim 10, wherein

said semiconductor substrate is an SOI substrate.