Dielectric relaxation memory
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Accused Products
Abstract
A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.
96 Citations
37 Claims
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1-26. -26. (canceled)
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27. A method of operating a memory device comprising the acts of:
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applying a first voltage to an electrode of a capacitor structure;
reading out a current from the capacitor structure;
applying a second voltage to an electrode of a capacitor structure, wherein the second voltage is greater than the first voltage such that the second voltage causes charge trap sites located within a dielectric layer of the capacitor structure to fill with charge; and
reading out a second current from the capacitor structure. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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34. A method of operating a memory device comprising the acts of:
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applying a first condition to a capacitor structure, wherein the first condition represents a first memory state;
reading out a current from the capacitor structure representing the first condition;
applying a second condition to the capacitor structure, wherein the second condition causes charge trap sites located within a dielectric layer of the capacitor structure to fill with charge and represents a second memory state; and
reading out a second current from the capacitor structure representing the second condition. - View Dependent Claims (35, 36, 37)
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Specification