Insulation film semiconductor device and method

• US 20060163641A1
• Filed: 11/04/2005
• Published: 07/27/2006
• Est. Priority Date: 11/05/2004
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Okumura, Yoichi
• Application Number:
  US11/266,988
• Publication Number:
  US 20060163641A1
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

A semiconductor device and method of its manufacturing method are provided for realizing smaller low voltage transistors while maintaining the characteristics of high voltage transistors. A first transistor formation region is separated by selectively leaving first element-separating insulator film. A second transistor formation region is separated by selectively oxidized second element-separating insulator film. On the region separated by first element-separating insulator film, a first transistor having a first channel-formation region, first source/drain regions, and first gate-insulation film with a first film thickness and first gate electrode are formed. On the region separated by second element-separating insulator film, second transistors having a second channel-formation region, second source/drain region second gate-insulation film with thickness thinner than the first film thickness, and a second gate electrode are formed.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a first element-separating insulator film that is formed and selectively left on the semiconductor substrate so as to perform element separation for the first transistor-formation region;

a second element-separating insulator film that is formed by selective oxidation of the surface layer of the semiconductor substrate so as to perform element separation for the second transistor-formation region;

a first transistor that is formed in the region separated by the first element-separating insulator film and has a first channel-formation region and a first source/drain region formed on the semiconductor substrate, a first gate-insulation film with the first film thickness formed on the first channel-formation region, and a first gate electrode formed on the first gate-insulation film; and

and a second transistor that is formed in the region separated by the second element-separating insulator film and has a second channel-formation region and a second source/drain region formed on the semiconductor substrate, a second gate-insulation film with a second film thickness less than the first film thickness and formed on the second channel-formation region, and a second gate electrode formed on the second gate-insulation film.

2. The device of claim 1, wherein the first gate-insulation film and the second element-separating insulator film have substantially the same film thickness.

3. The device of claim 1, wherein the first transistor is a high voltage transistor and the second transistor is a low voltage transistor.

4. The device of claim 1, wherein a back gate region is formed adjacent to the first source/drain region.

5. The device of claim 1, wherein, as the second transistor, a transistor of the first electroconductive type and a transistor of the second electroconductive type are formed.

6. The device of claim 1, wherein, in the region separated by the first element-separating insulator film, there is also a third transistor that has a second channel-formation region and a third source/drain region formed on the semiconductor substrate, a second gate-insulation film with film thickness less than the first film thickness and formed on the third channel-formation region, and a third gate electrode formed on the third gate-insulation film.

7. The device of claim 1, wherein the semiconductor substrate is a substrate having an SOI (semiconductor on insulator) structure having a semiconductor layer on an insulating film on the substrate.

8. The device of claim 7, wherein, on the substrate of the SOI structure, the region of the semiconductor layer where the first transistor is formed is individually insulated and separated by an insulating layer formed from the surface of the semiconductor layer to reach the insulating film.

9. A method for manufacturing a semiconductor device characterized by the following operation steps:

a step in which the first transistor-formation region of the semiconductor substrate having the first channel-formation region is selectively left for element separation to form the first element-separating insulator film;

a step in which the surface layer portion of the semiconductor substrate is selectively oxidized for element separation of the second transistor-formation region of the semiconductor substrate having the second channel-formation region to form the second element-separating insulator film;

a step in which the first gate-insulation film with the first film thickness is formed on the surface of the semiconductor substrate in the first transistor-formation region;

a step in which the second gate-insulation film with the second film thickness less than the second film thickness is formed on the surface of the semiconductor substrate in the second transistor-formation region;

a step in which the first gate electrode is formed on the first gate-insulation film, and the second gate electrode is formed on the second gate-insulation film; and

a step in which the first source/drain region connected to the first channel-formation region is formed, and the second source/drain region connected to the second channel-formation region is formed.

10. The method of claim 9, wherein the step of forming the second element-separating insulator film and the step of forming the first gate-insulation film are carried out simultaneously.

11. The method of claim 9, wherein t the step of forming the first element-separating insulator film includes the following operation steps:

a step in which an insulating film is formed on the entire surface of the semiconductor substrate,

a step in which the first mask layer for protecting the formation region of the first element-separating insulator film is formed on the insulating film,

and a step in which the first mask layer is used to perform patterning processing for the insulating film so as to selectively leave it in the formation region of the first element-separating insulator film to form the first element-separating insulator film.

12. The method of claim 9, wherein the step of forming the second element-separating insulator film includes the following operation steps:

a step in which the second mask layer protecting the region excluding the formation region of the second element-separating insulator film is formed on the semiconductor substrate, and

a step in which the surface layer portion of the semiconductor substrate in the formation region of the second element-separating insulator film exposed from the second mask layer is selectively oxidized to form the second element-separating insulator film.

13. The method of claim 9, wherein the step of forming the first gate-insulation film includes the following operation steps:

a step in which the first gate-insulation film is formed,

a step in which the second mask layer protecting the region excluding the first transistor formation region is formed on the semiconductor substrate,

and a step in which the surface layer portion of the semiconductor substrate in the first transistor formation region exposed from the second mask layer is selectively oxidized to form the first gate-insulation film.