Power semiconductor device with endless gate trenches

• US 20060163650A1
• Filed: 01/24/2006
• Published: 07/27/2006
• Est. Priority Date: 01/27/2005
• Status: Abandoned Application

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Ma, Ling
• Application Number:
  US11/338,215
• Publication Number:
  US 20060163650A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device which includes endless gate trenches.

Claims

1. A power semiconductor device comprising:

a drift region of a first conductivity;

a base region of a second conductivity over said drift region;

a plurality of endless trenches extending through said base region to said drift region;

a gate insulation layer formed in each endless trench adjacent said base region; and

a gate electrode residing in each endless trench.

2. The power semiconductor device of claim 1, wherein each said endless trench includes two spaced parallel trenches and two connecting trenches connecting said two parallel trenches to form an endless trench.

3. The power semiconductor device of claim 2, wherein said connecting trenches are curved.

4. The power semiconductor device of claim 2, further comprising a gate bus disposed over at least a portion of one of said connecting trenches and electrically connected to said gate electrode.

5. The power semiconductor device of claim 1, wherein said gate electrode is comprised of conductive polysilicon.

6. The power semiconductor device of claim 1, wherein said gate insulation is comprised of silicon dioxide.

7. The power semiconductor device of claim 1, wherein each said endless trench includes a curved bottom portion.

8. The power semiconductor device of claim 1, further comprising an insulation body disposed at the bottom of each endless trench, said insulation body being thicker than said gate insulation.

9. The power semiconductor device of claim 1, further comprising conductive regions of said first conductivity over said body region and adjacent said each endless trench.

10. The power semiconductor device of claim 1, wherein said drift region is disposed over a substrate.

11. The power semiconductor device of claim 10, wherein said substrate is comprised of silicon.

12. The power semiconductor device of claim 1, wherein said power semiconductor device is a MOSFET.

13. The power semiconductor device of claim 1, wherein said power semiconductor device is an IGBT.

14. A power semiconductor device comprising:

a plurality of spaced endless gate trenches each including two opposing and spaced trenches connected to one another by connecting trenches to form an endless gate trench;

a gate insulation liner lining at least the walls of said endless trenches;

an endless gate electrode disposed within each endless trench; and

a voltage supply bus electrically connected to each of said endless gate electrodes.

15. The power semiconductor device of claim 14, wherein each endless gate trench is spaced from another endless gate trench by an active region and each endless gate trench includes an active region residing within an interior region thereof.

16. The power semiconductor device of claim 14, wherein said connecting trenches are curved.

17. The power semiconductor device of claim 14, wherein each active region includes a conductive region of first conductivity adjacent a respective gate trench and a high conductivity of second conductivity disposed between said conductive regions of said first conductivity.

18. The power semiconductor device of claim 16, further comprising a gate bus residing over at least a portion of one of said connecting portions and electrically connected to said gate electrode disposed within said endless gate trench.

19. The power semiconductor device of claim 14, wherein each endless gate trench includes a curved bottom.