Flip chip interconnection pad layout

• US 20060163715A1
• Filed: 03/10/2006
• Published: 07/27/2006
• Est. Priority Date: 11/08/2003
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Chippac Company Limited
• Inventors: Pendse, Rajendra D.
• Granted Patent: US 7,605,480 B2
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Claims

1. A semiconductor package, having a semiconductor chip mounted in a flip chip configuration on a substrate, the semiconductor chip having a die pad layout having signal pads located primarily near the perimeter of the die, and having ground and power pads located primarily inboard from the signal pads.

2. The package of claim 1 wherein the signal pads are arranged primarily in a peripheral row generally parallel to a die edge.

3. The package of claim 1 wherein the signal pads are arranged primarily in a peripheral array, generally parallel to a die edge.

4. The package of claim 3 wherein the signal pads are arranged primarily in at least two rows parallel to a die edge.

5. The package of claim 4 wherein the signal pads in adjacent rows are in a staggered arrangement.

6. The package of claim 4 wherein the signal pads in adjacent rows are in an orthogonal arrangement.

7. The package of claim 1 wherein the power/ground pads are arranged primarily in an array near the center of the die.

8. The package of claim 7 wherein the power/ground pads are arranged primarily in a rectangular array.

9. The package of claim 7 wherein a central area of the die has no pads.

10. The package of claim 1 wherein the power/ground pads are arranged primarily inboard from and near the signal pads.

11. The package of claim 1 wherein the power/ground pads are arranged primarily in a row parallel to a die edge inboard from and near the signal pads.

12. The package of claim 10 wherein the power/ground pads are arranged primarily in an array parallel to a die edge inboard from and near the signal pads.

13. The package of claim 12 wherein the power/ground pads are primarily arranged in at least two rows parallel to a die edge inboard from and near the signal pads.

14. The package of claim 13 wherein the ground/power pads in adjacent rows are in a staggered arrangement.

15. The package of claim 13 wherein the ground/power pads in adjacent rows are in an orthogonal arrangement.

16. A semiconductor package, having a semiconductor chip mounted in a flip chip configuration on a substrate, the semiconductor chip having a die pad layout having signal pads disposed primarily in a perimeter region near an edge of the die, and having power/ground pads disposed primarily in an inboard region.

17. The package of claim 16 wherein fewer than 10% of the power/ground pads are located within the perimeter region.

18. The package of claim 16 wherein fewer than 5% of the power/ground pads are located within the perimeter region.

19. The package of claim 16 wherein fewer than 2% of the power/ground pads are located within the perimeter region.

20. The package of claim 16 wherein none of the power/ground pads is located within the perimeter region.

21. The package of claim 16 wherein fewer than 10% of the signal pads are located within the inboard region.

22. The package of claim 16 wherein fewer than 5% of the signal pads are located within the inboard region.

23. The package of claim 16 wherein fewer than 2% of the signal pads are located within the inboard region.

24. The package of claim 16 wherein none of the signal pads is located within the inboard region.

25. A semiconductor package comprising a semiconductor chip mounted on a substrate, the substrate comprising a die attach region including a die footprint, having signal pads located primarily in the margin of the die footprint, and having signal escape lines running in an upper metal layer outwardly and away from the die footprint, and having power pads and ground pads located primarily inwardly from the signal pads and ground and signal lines dropping through vias to lower metal layers.

26. The package of claim 25 wherein the signal pads are arranged primarily in a row generally parallel to the edge of the die footprint.

27. The package of claim 25 wherein the signal pads are arranged primarily in an array.

28. The package of claim 25 wherein the signal pads are arranged in two or more rows generally parallel to the edge of the die footprint.

29. The package of claim 28 wherein the pads in adjacent rows are staggered.

30. The package of claim 28 wherein the pads in adjacent rows are arranged orthogonally.

31. The package of claim 25 wherein the power/ground pads are arranged primarily in an array near the center of the die attach region.

32. The package of claim 31 wherein the power/ground pads are arranged primarily in a rectangular array.

33. The package of claim 31 wherein a central area of the die attach region has no pads.

34. The package of claim 25 wherein the power/ground pads are arranged primarily inwardly from and near the signal pads.

35. The package of claim 25 wherein the power/ground pads are arranged primarily in a row parallel to a margin of the die footprint inward from and near the signal pads.

36. The package of claim 25 wherein the power/ground pads are arranged primarily in an array parallel to a margin of the die footprint inward from and near the signal pads.

37. The package of claim 36 wherein the power/ground pads are primarily arranged in at least two rows parallel to a margin of the die footprint inward from and near the signal pads.

38. The package of claim 37 wherein the ground/power pads in adjacent rows are in a staggered arrangement.

39. The package of claim 37 wherein the ground/power pads in adjacent rows are in an orthogonal arrangement.

40. A semiconductor package comprising a semiconductor chip mounted on a substrate, the substrate comprising a die attach region including a die footprint, having signal pads disposed primarily in perimeter region of the die footprint, and having signal escape lines running in an upper metal layer outwardly and away from the die footprint, and having power/ground pads disposed primarily in an inboard region inward from the signal pads and ground and power lines dropping through vias to lower metal layers.

41. The package of claim 40 wherein fewer than 10% of the power/ground pads are located within the perimeter region.

42. The package of claim 40 wherein fewer than 5% of the power/ground pads are located within the perimeter region.

43. The package of claim 40 wherein fewer than 2% of the power/ground pads are located within the perimeter region.

44. The package of claim 40 wherein none of the power/ground pads is located within the perimeter region.

45. The package of claim 40 wherein fewer than 10% of the signal pads are located within the inboard region.

46. The package of claim 40 wherein fewer than 5% of the signal pads are located within the inboard region.

47. The package of claim 40 wherein fewer than 2% of the signal pads are located within the inboard region.

48. The package of claim 40 wherein none of the signal pads is located within the inboard region.