IC chip package structure and underfill process

• US 20060163749A1
• Filed: 01/25/2005
• Published: 07/27/2006
• Est. Priority Date: 01/25/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Hsin-Hui, Lee, Chien-Hsiun
• Granted Patent: US 7,148,560 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.

Claims

1. An integrated circuit chip structure comprising:

a carrier substrate;

a flip chip provided on said substrate;

a dam structure provided on said carrier substrate; and

an adhesive material provided between said carrier substrate and said flip chip.

2. The integrated circuit chip structure of claim 1 wherein said adhesive material comprises an epoxy resin.

3. The integrated circuit chip structure of claim 1 wherein said carrier substrate comprises a printed circuit board.

4. The integrated circuit chip structure of claim 3 wherein said adhesive material is a high stress modulus material.

5. The integrated circuit chip structure of claim 1 wherein said adhesive material is injected at a plurality of injection points at a plurality of edges, respectively, of said flip chip.

6. The integrated circuit chip structure of claim 1 wherein said dam structure comprises an epoxy resin.

7. The integrated circuit chip structure of claim 1 wherein said dam structure is disposed adjacent to respective corners of said flip chip.

8. The integrated circuit chip structure of claim 1 wherein said dam structure comprises a plurality of dam elements.

9. An integrated circuit chip structure comprising:

a carrier substrate and a generally rectangular flip chip provided on said carrier substrate;

a dam structure provided on said carrier substrate;

an adhesive material provided between said carrier substrate and said flip chip; and

a sealant material provided around said adhesive material.

10. The integrated circuit chip structure of claim 9 wherein said adhesive material comprises an epoxy resin.

11. The integrated circuit chip structure of claim 9 wherein said carrier substrate comprises a printed circuit board.

12. The integrated circuit chip structure of claim 9 wherein said adhesive material is injected at three injection points at three edges of said flip chip.

13. The integrated circuit chip structure of claim 9 wherein said dam structure comprises a plurality of dam elements provided at respective corners of said flip chip and wherein each of said dam elements comprises an epoxy resin.

14. The integrated circuit chip structure of claim 9 wherein said sealant comprises an epoxy resin comprising rosen.

15. The integrated circuit chip structure of claim 9 wherein said dam structure comprises an epoxy resin.

16. The integrated circuit chip structure of claim 9 wherein said dam structure comprises a plurality of dam elements having an L-shaped configuration.

17. An integrated circuit chip structure, comprising:

a carrier substrate;

a plurality of dam elements provided on said carrier substrate;

a flip chip attached to said carrier substrate, with respective corners of said flip chip disposed adjacent to said dam elements, respectively;

an adhesive material provided between said carrier substrate and said flip chip; and

a sealant material provided around said adhesive material.

18. The integrated circuit chip structure of claim 17 wherein said adhesive material comprises an epoxy resin.

19. The integrated circuit chip structure of claim 17 wherein said carrier substrate comprises a printed circuit board.

20. The integrated circuit chip structure of claim 17 wherein each of said dam elements comprises a pair of element segments disposed in generally perpendicular relationship to each other.