Compensation technique providing stability over broad range of output capacitor values

• US 20060164053A1
• Filed: 01/21/2005
• Published: 07/27/2006
• Est. Priority Date: 01/21/2005
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Panganiban, Joseph Sinohin, Walter, William Louis
• Granted Patent: US 7,218,082 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A disclosed amplifier and buffer circuit, for example for a linear voltage regulator, comprises an input gain stage, an integrator and a unity-gain output stage. An output stage compensation scheme enables stable operation over a broad range of output capacitance. For low to moderate output capacitance, the design of the output stage effectively pushes the output pole to high frequencies while an internal pole provided by the integrator is dominant and rolls off the gain at lower frequencies. For high output capacitance, an input impedance of the buffer couples the internal pole and output pole, such that the output pole becomes dominant while the internal pole gets pushed to higher frequencies, maintaining stability. This input impedance connection may utilize the base-emitter resistance of a bipolar junction transistor connected to the internal node, or the connection may use an MOS transistor and a separate R_C circuit.

Claims

1. A voltage regulator receiving an input voltage and operative over a specified range of output capacitances at a load comprising:

a control circuit responsive to load voltage for generating an error signal indicative of a difference thereof from a reference voltage; and

an output stage responsive to the error signal for providing regulated voltage to the load, the output stage comprising;

(a) a metal oxide semiconductor (MOS) pass transistor having a source and a drain coupled between an input voltage source and the load and having a gate for controlling voltage drop across the MOS pass transistor to provide the regulated voltage at the load; and

(b) an input transistor circuit responsive to the error signal and coupled to control operation of the MOS pass transistor, the input transistor circuit presenting a shunt impedance to the error signal for values of output capacitances within a portion of the range of output capacitances so as to stabilize closed loop gain of the voltage regulator for output capacitances within that portion.

2. The voltage regulator as in claim 1, wherein:

the input transistor circuit comprises a bipolar junction transistor (BJT) having a base receiving the error signal; and

the base-emitter resistance of the BJT provides the shunt impedance for the values of output capacitances within the portion of the range of output capacitances.

3. The voltage regulator as in claim 2, wherein:

the output stage comprises at least one current mirror circuit responsive to operation of the BJT transistor, coupled between a source of the input voltage and the load, and

the MOS pass transistor is an element of at least one current mirror circuit.

4. The voltage regulator as in claim 3, wherein at least one current mirror circuit comprises a PMOS current mirror and an NMOS current mirror.

5. The voltage regulator as in claim 3, wherein:

the control circuit includes an integrator for supplying the error signal to the base of the BJT transistor, and

the emitter of the BJT transistor is connected to a node of the output stage supplying the regulated voltage to the load.

6. The voltage regulator as in claim 1, wherein the input transistor circuit comprises:

a metal oxide semiconductor (MOS) transistor having a gate receiving a signal related to the error signal; and

a series resistance and capacitance, forming the shunt impedance, connected to the gate of the MOS transistor of the input transistor circuit.

7. The voltage regulator as in claim 6, wherein:

the output stage comprises at least one current mirror circuit responsive to operation of the MOS transistor of the input transistor circuit, coupled between the input voltage and the load, and

the MOS pass transistor is an element of the at least one current mirror circuit.

8. The voltage regulator as in claim 7, wherein:

the at least one current mirror circuit comprises a PMOS current mirror and an NMOS current mirror, and

the MOS pass transistor comprises an NMOS transistor of the NMOS current mirror.

9. The voltage regulator as in claim 8, wherein the MOS transistor of the input transistor circuit is an NMOS transistor.

10. The voltage regulator as in claim 1, wherein:

the control circuit comprises a transconductance amplifier; and

the output stage provides unity gain.

11. The voltage regulator as in claim 10, wherein the control circuit further comprises an integrator coupled between an output of the transconductance amplifier and the input transistor circuit.

12. The voltage regulator as in claim 1, wherein the output stage comprises at least one resistor-transistor circuit.

13. The voltage regulator as in claim 12, wherein the MOS pass transistor is an element of the at least one resistor-transistor circuit.

14. The voltage regulator as in claim 13, wherein the at least one resistor-transistor circuit containing the MOS pass transistor also includes a low impedance transistor-follower circuit coupled to drive the gate of the MOS pass transistor.

15. A voltage regulator, comprising:

a control circuit for monitoring a voltage proportional to a load voltage and generating an error signal indicative of a difference thereof from a reference voltage; and

an output stage responsive to the error signal for providing a regulated voltage to the load, the output stage comprising;

(a) a metal oxide semiconductor (MOS) pass transistor having a source and a drain coupled between a source of the input voltage and the load and having a gate for controlling voltage drop across the MOS pass transistor to provide regulated voltage to the load; and

(b) an input transistor comprising a bipolar junction transistor (BJT) having a base receiving the error signal and being coupled to control the MOS pass transistor.

16. The voltage regulator as in claim 15, wherein:

the output stage comprises at least one current mirror circuit responsive to operation of the BJT transistor, coupled between the source of input voltage and the load, and

the MOS pass transistor comprises an element of at least one current mirror circuit.

17. The voltage regulator as in claim 16, wherein the at least one current mirror circuit comprises a PMOS current mirror and an NMOS current mirror.

18. The voltage regulator as in claim 15, wherein:

the control circuit comprises a transconductance amplifier; and

the output stage provides unity gain.

19. The voltage regulator as in claim 18, wherein the control circuit further comprises an integrator coupled between an output of the transconductance amplifier and the base of the BJT transistor.

20. The voltage regulator as in claim 15, wherein:

the output stage comprises at least one resistor-transistor circuit; and

the MOS pass transistor is an element of at least one resistor-transistor circuit.

21. The voltage regulator as in claim 20, wherein the at least one resistor-transistor circuit containing the MOS pass transistor also includes a low impedance transistor-follower circuit coupled to drive the gate of the MOS pass transistor.

22. A voltage regulator operative over a specified range of output capacitances comprising:

an amplifier coupled to receive regulated load voltage;

an integrator responsive to an output of the amplifier for providing an error signal, wherein the integrator is configured to stabilize closed loop gain of the voltage regulator for output capacitance values within a first portion of the specified range of output capacitances; and

a unity gain output stage coupled to an input voltage source for supplying the regulated voltage to the load in response to the error signal,

wherein the unity gain output stage is configured to stabilize the closed loop gain of the voltage regulator for output capacitance values in a second portion of the specified range of capacitance values higher than the first portion.

23. A circuit coupled to an input signal source and configured for responsively producing an output signal, comprising:

a greater than unity gain amplifier coupled to the output signal;

an integrator coupled to an output of the amplifier; and

an output stage buffer for processing the input signal in response to a signal from the integrator, to supply the output signal to a load, wherein;

the integrator is configured to stabilize the closed loop gain of the circuit over a first portion of a specified range of load capacitances; and

the output stage buffer is configured to stabilize closed loop gain of the circuit over a second portion of the specified range of capacitances higher than the first portion.

24. The circuit of claim 23, wherein the output stage buffer comprises:

(a) a pass transistor, coupled between the input signal and the load and having an input, for controlling the voltage drop across the pass transistor to provide the output signal at the load; and

(b) a stabilizing circuit, responsive to the signal from the integrator and coupled to the pass transistor, for stabilizing the output signal over the range of output capacitance.

25. The circuit as in claim 24, wherein the stabilizing circuit comprises an input transistor circuit responsive to the signal from the integrator and configured to shunt the signal from the integrator, for a portion of the range of output capacitance.

26. The circuit as in claim 25, wherein the stabilizing circuit further comprises:

a first current mirror circuit coupled between the input transistor circuit and a bias voltage for providing a first current gain; and

a transistor coupled to the pass transistor to form a second current mirror, responsive to a current from the first current mirror, and coupled between the input signal and the load to provide a second current gain.

27. The circuit as in claim 26, wherein:

the input transistor circuit comprises a bipolar junction transistor (BJT) having a base receiving the signal from the integrator, a collector coupled to the first current mirror and an emitter coupled to the output signal at the load, a base-emitter resistance of the BJT transistor providing the shunt of the signal from the integrator; and

the pass transistor comprises a metal oxide semiconductor (MOS) transistor.

28. The circuit as in claim 25, wherein:

the input transistor circuit comprises a metal oxide semiconductor (MOS) transistor, and a shunt circuit coupled to shunt the signal from the integrator around the MOS transistor for the portion of the range of output capacitance; and

the pass transistor comprises a MOS transistor.

29. The circuit as in claim 28, wherein the shunt circuit comprises series connected resistance and capacitance.

30. The circuit as in claim 24, wherein:

the stabilizing circuit comprises at least one resistor-transistor circuit; and

the pass transistor is an element of the at least one resistor-transistor circuit.

31. The circuit as in claim 30, wherein the at least one resistor-transistor circuit containing the pass transistor further includes a low impedance transistor-follower circuit coupled to drive the input of the pass transistor.

32. A circuit operative throughout a specified range of output capacitances, and supplying an output signal to a load, comprising:

an amplifier for monitoring a voltage proportional to the output signal load to generate an error signal indicative of a difference thereof from a reference voltage; and

a buffer, responsive to the error signal, to supply the output signal, the buffer comprising;

(a) a metal oxide semiconductor (MOS) pass transistor having a source and a drain coupled between the input signal and the load and having a gate for controlling voltage drop across the MOS pass transistor; and

(b) an input transistor circuit responsive to the error signal, coupled to control operation of the MOS pass transistor, the input transistor circuit presenting a shunt impedance to the error signal for values of output capacitances in a portion of the range of output capacitances so as to stabilize closed loop gain over that portion of the range.

33. The circuit as in claim 32, wherein:

the input transistor circuit comprises a bipolar junction transistor (BJT) having a base receiving the error signal; and

the base-emitter resistance of the BJT provides the shunt impedance for values of output capacitance in the portion of the range.

34. The circuit as in claim 32, wherein the input transistor circuit comprises:

a metal oxide semiconductor (MOS) transistor having a gate receiving the error signal; and

a series resistance and capacitance forming the shunt impedance for values of output capacitances in the portion of the range of output capacitances.

35. The circuit as in claim 32, wherein:

the amplifier comprises a transconductance amplifier; and

the output stage buffer is of unity gain.

36. The circuit as in claim 35, further comprising an integrator coupled to an output of the transconductance amplifier for supplying the error signal to the input transistor circuit.

37. The circuit as in claim 32, wherein:

the output stage buffer comprises at least one resistor-transistor circuit; and

the MOS pass transistor is an element of at least one resistor-transistor circuit.

38. The circuit as in claim 37, wherein the at least one resistor-transistor circuit containing the MOS pass transistor further includes a low impedance transistor-follower circuit coupled to drive the gate of the MOS pass transistor.

39. A circuit for supplying an output signal to a load, comprising:

an amplifier for monitoring a voltage proportional to the output signal, to generate an error signal indicative of a difference thereof from a reference voltage;

an integrator coupled to receive the error signal and producing an integrated error signal;

an output stage responsive to the integrated error signal for producing the output signal, the output stage comprising;

(a) a metal oxide semiconductor (MOS) pass transistor having a source and a drain coupled between the input signal and the output and having a gate for controlling voltage drop across the MOS pass transistor to provide the output signal; and

(b) a bipolar junction transistor (BJT) having a base receiving the integrated error signal, coupled to control operation of the MOS pass transistor.