High resolution pulse width modulator

• US 20060164142A1
• Filed: 01/21/2005
• Published: 07/27/2006
• Est. Priority Date: 01/21/2005
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Stanley, Michael E.
• Granted Patent: US 7,288,977 B2
• Time in Patent Office: Days
• US Class Current: 327/172
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A pulse width modulator (100) and method that facilitates high resolution pulse width modulation is provided. The pulse width modulator (100) creates a pulse width modulated signal having a duty cycle that is proportional to a controllable delay in the modulator. The pulse width modulator combines a first digitally controllable delay (102) with a delay adjustment (104) to provide the controllable delay. In one embodiment, a digital counter (202) is used to provide coarse delay, with the delay adjustment device (210) coupled to the digital counter (202) to provide the fine, high resolution, delay control. Together the digital counter (202) and delay adjustment device (210) provide high resolution pulse width modulation. In one particular implementation, the analog delay adjustment device (100) comprises a delay block (500) designed to provide delay adjustment that is selectively controllable by changing a capacitance in the device.

Claims

1. A pulse width modulator, the pulse width modulator comprising:

a fist delay device, the first delay device adapted to create a first delay;

a delay adjustment device, the delay adjustment device adapted to create second delay, wherein the delay adjustment device comprises a delay block, and wherein the delay block includes a first capacitor and a variable capacitor having a variable capacitance, and wherein the delay block is adapted to store a first voltage on the first capacitor, and wherein the delay block is adapted to determine the second delay by controllably varying the variable capacitance, charging the variable capacitor to a second voltage and comparing the second voltage on the variable capacitor to the first voltage on the first capacitor such that the second delay is determined at least in part by the controllably varied variable capacitance;

a signal generating device coupled to the first delay device and the delay adjustment device, the signal generating device adapted to create a pulse width modulated signal having a duty cycle responsive to a combination of the first delay and the second delay.

2. The modulator of claim 1 wherein the first delay device comprises a counter.

3. The modulator of claim 1 wherein the signal generating device comprises a flip-flop.

7. The modulator of claim 1 wherein the delay block stores the first voltage on the first capacitor by charging the first capacitor using a current source coupled to the first capacitor for a determined precharge time period.

8. The modulator of claim 7 wherein the determined precharge time period is equal to one-half a clock period.

9. The modulator of claim 7 wherein the first capacitor is coupled to the current source through a current source switch.

10. The modulator of claim 1 wherein the delay block charges the variable capacitor using a second current source coupled to the variable capacitor.

11. The modulator of claim 1 wherein the delay block includes a first switch to selectively discharge the first capacitor.

12. The modulator of claim 1 wherein the delay block includes a second switch to selectively discharge the variable capacitor.

5. (canceled)

6. (canceled)

4. The modulator of claim 6 wherein the variable capacitor comprises an army of switched capacitors coupled together to provide the variable capacitance.

13. A pulse width modulator, the pulse width modulator comprising:

a first delay device, the first delay device creating a first delay;

a delay adjustment device, the delay adjustment device creating a second delay using a delay block and wherein the delay block includes;

a first capacitor, the first capacitor coupled to a first current source, wherein the delay block stores a first voltage on the capacitor by charging Me first capacitor with the first current source for a determined precharge time period;

a variable capacitor, the variable capacitor coupled to a second current source, and wherein the delay block determines the second delay by charging the variable capacitor and comparing the voltage on the variable capacitor to the first voltage, and wherein the second delay is adjusted by adjusting the variable capacitor; and

a signal generating device coupled to the first delay device and the delay adjustment device, the signal generating device creating a pulse width modulated signal having a duty cycle proportional to the first delay plus the second delay.

14. The modulator of claim 13 wherein the first delay device comprises a counter and a comparator, and wherein the counter provides a count value to the comparator, and wherein the comparator provides an output used to determine when to start charging the first capacitor.

15. The modulator of claim 13 wherein the first delay device comprises a counter and wherein the counter provides a count value to the delay adjustment device, and wherein the count value is used to determine when to start charging the first capacitor.

16. The modulator of claim 13 wherein the signal generating device comprises a flip-flop.

17. The modulator of claim 13 wherein the delay block includes a first switch to selectively discharge the first capacitor, a second switch to selectively discharge the variable capacitor, and wherein the first capacitor is coupled to the current source through a current source switch.

18. The modulator of claim 13 wherein the variable capacitor comprises a switched capacitor circuit having a digitally selected capacitance.

19. A method of generating a pulse width modulated signal, the method comprising the steps of:

creating a first delay;

controllably varying a variable capacitance of a variable capacitor;

storing a first voltage on a first capacitor;

charging the variable capacitor to a second voltage;

comparing the first voltage to the second voltage to create a second delay such that the second delay is determined at least in part by the variable capacitance; and

generating a pulse width modulated signal having a duty cycle responsive to a combination of the first delay plus the second delay.

20. The method of claim 19 wherein the step of controllably varying a variable capacitance of a variable capacitor comprises controllably varying an array of switched capacitors coupled together to provide the variable capacitance.