Liquid crystal display and driving method thereof

• US 20060164380A1
• Filed: 10/21/2005
• Published: 07/27/2006
• Est. Priority Date: 01/21/2005
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: Chi Mei Innolux Corporation (InnoLux Corporation)
• Inventors: Yang, Chia-Ho, Yang, Hui-Wen
• Granted Patent: US 7,696,975 B2
• Time in Patent Office: Days
• US Class Current: 345/103
• CPC Class Codes: G09G 2310/062 Waveforms for resetting a plurality of scan lines at a time
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A liquid crystal display includes an active display area and gate drivers. The active display area includes display blocks, each display block including pixel rows. The gate driver sequentially outputs gate signals to the display block and drives corresponding pixel rows to display pixel images, or outputs a dummy gate signal to the display block to drive the corresponding pixel rows to display a compensation image for improving motion image quality. A method of driving the liquid crystal display includes using the gate drivers to sequentially drive the pixel rows of each of the display blocks to display pixel images, and using the gate driver to output a dummy gate signal to simultaneously drive the pixel rows of another display block to display the compensation image.

Claims

1. A display comprising:

an active display area comprising a plurality of display blocks, each display block comprising a plurality of pixel rows; and

a gate driver for sending a plurality of normal gate signals to the display blocks to drive corresponding pixel rows to display a normal image, the gate driver also sending a dummy gate signal to each display block to simultaneously drive the pixel rows of the display block to display a compensation image.

2. The display of claim 1, wherein after pixel rows of one display block receive corresponding normal gate signals to display the normal image, the pixel rows of another display block receive a corresponding dummy gate signal to display the compensation image.

3. The display of claim 1, further comprising a plurality of multiplexers, wherein each multiplexer sequentially outputs the normal gate signals to pixel rows of a corresponding display block and outputs the dummy gate signal for all the pixel rows of the corresponding display block.

4. The display of claim 3, wherein each multiplexer comprises a plurality of transistor sets for driving the pixel rows of the corresponding display block, each transistor set comprising a first transistor and a second transistor, in which the gate of the first transistor receives one of the normal gate signals, and the gate of the second transistor receives the dummy gate signal.

5. The display of claim 4, wherein the transistors are NMOS transistors, and each normal gate signal and dummy gate signal provides high level voltages.

6. The display of claim 1, wherein the active display area comprises m display blocks, each display block comprising k pixel rows, m and k being positive integers larger than 1, and wherein after the gate driver generates normal gate signals to drive a p-th display block, the gate driver generates a dummy signal to drive a {mod((p+i),m)+1}-th display block, 1≦

p≦

m, 1≦

i<

m, p and i being positive integers.

7. The display of claim 1, wherein each dummy gate signal drives the pixel rows of a display block to receive a zero gray level voltage signal from a data driver.

8. The display of claim 1, wherein each dummy gate signal drives a display block during a blanking time.

9. A display, comprising:

a plurality of display blocks, each display block comprising a plurality of pixel rows;

a plurality of gate drivers, each for sequentially outputting a plurality of normal gate signals to drive the pixel rows to display a normal image on a display block, or outputting a plurality of dummy gate signals simultaneously to the display block to drive the pixel rows to display a compensation image; and

a timing controller for outputting a plurality of control signals to control the gate drivers, some of the control signals for controlling the gate drivers to output a plurality of dummy gate signals simultaneously.

10. The display of claim 9, wherein after one gate driver sequentially outputs the normal gate signals to drive a corresponding display block to display a normal image, the timing controller outputs a control signal to another gate driver to cause the other gate driver to simultaneously output a plurality of dummy gate signals to drive the corresponding display block to display the compensation image.

11. The display of claim 9, wherein the display blocks comprise m display blocks, each display block comprising k pixel rows, m and k being positive integers larger than 1, and wherein after the p-th display block is driven by the normal gate signals, a {mod((p+i),m)+1}-th display block is driven by a dummy gate signal, 1≦

p≦

m, 1≦

i<

m, p, i being positive integers.

12. The display of claim 9, wherein each dummy gate signal drives the pixel rows of a display block to simultaneously receive a zero gray level voltage signal.

13. A method for driving a display having an active display area that includes display blocks, each display block including pixel rows, the method comprising:

sequentially driving the pixel rows of a display block to display a normal image, and

driving another display block to display a compensation image.

14. The method of claim 13, wherein driving another display block to display a compensation image comprises simultaneously driving the pixel rows of the other display block to display the compensation image.

15. The method of claim 14, further comprising, at the pixel rows driven to display the compensation image, simultaneously receiving a zero gray level voltage signal.

16. The method of claim 13, wherein the active display area includes m display blocks, each display block including k pixel rows, m and k being positive integers larger than 1, and the step of driving the pixel rows of each display block comprises driving a {mod((p+i),m)+1}-th display block to display the compensation image after driving the p-th display block to display a normal image, 1≦

p≦

m, 1≦

i<

m, p, i being positive integers.

17. The method of claim 16, wherein an increase in the number m corresponds to a decrease in a difference between duty ratios of the first and k-th pixel rows in a display block.

18. A method for driving a display that includes display blocks and gate drivers, each display block including pixel rows, the method comprising:

controlling a first gate driver to sequentially drive pixel rows of a first display block to display a normal image; and

controlling a second gate driver to simultaneously drive the pixel rows of a second display block to display a compensation image.

19. The method of claim 18, wherein the display areas comprise m display blocks, each display block comprising k pixel rows, m and k being positive integers larger than 1, and the method comprises driving a {mod((p+i),m)+1}-th display block to display a compensation image after driving a p-th display area to display a normal image, 1≦

p≦

m, 1≦

i<

m, p and i being positive integers.

20. The method of claim 18, wherein controlling the second gate driver to drive the pixel rows of the second display block comprises controlling the second gate driver to simultaneously output dummy gate signals to drive the pixel rows of the second display block to receive zero gray level voltage signals.

21. The method of claim 18, further comprising a timing controller to determine when the first gate driver drives the pixel rows of the first display block and when the second gate driver drives the pixel rows of the second display block.

22. An apparatus comprising:

an active display area comprising regions, each region comprising at least two rows of pixel circuits; and

at least one gate driver to output normal gate signals and dummy gate signals to drive the regions to display a normal image and a compensation image, respectively, in which the gate driver drives different rows of pixel circuits in a region at different times to display the normal image, and drives different rows of pixel circuits in a region at the same time to display the compensation image.

23. The apparatus of claim 22, further comprising multiplexers, each to select one of a normal gate signal and a dummy gate signal to drive a gate line coupled to a pixel circuit.

24. The apparatus of claim 22 in which the compensation image comprises a black image.

25. A display comprising:

pixel circuits;

gate lines for controlling the pixel circuits; and

multiplexers, each having at least two inputs to receive at least two gate signals, each multiplexer enabling one of the gate signals received at the multiplexer to control one of the gate lines.

26. The apparatus of claim 25 in which one of the gate signals received at a multiplexer controls pixel circuits to show a portion of a normal image, and another of the gate signals received at the multiplexer controls the pixel circuits to show a portion of a compensation image.

27. The apparatus of claim 26 in which at least two of the multiplexers simultaneously receive a common gate signal that controls pixel circuits to show portions of the compensation image.

28. The apparatus of claim 27 in which the compensation image comprises a black image

29. A method comprising:

driving different rows of pixels of a display at different times to display a portion of a normal image, and

driving the different rows of pixels simultaneously to display a portion of a compensation image.

30. The method of claim 29 in which the compensation image comprises a black image.

31. The method of claim 29 in which driving the rows of pixels to display a portion of the compensation image is performed during a blank period as defined by VESA (video electronics standard association) standard.

32. A method comprising:

receiving at least two gate signals at a multiplexer, and enabling one of the gate signals to drive a gate line of a display, the gate line coupled to pixel circuits.

33. The method of claim 32, in which one of the gate signals is associated with a normal image, and another of the gate signals is associated with a compensation image.

34. The method of claim 33 in which the compensation image comprises a black image.

35. The method of claim 32, further comprising receiving a gate signal associated with the compensation image at two multiplexers, and simultaneously driving two gate lines with the gate signal.